211 lines
8.5 KiB
Systemverilog
211 lines
8.5 KiB
Systemverilog
`include "VX_tex_define.vh"
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module VX_tex_addr #(
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parameter CORE_ID = 0,
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parameter REQ_INFOW = 1,
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parameter NUM_REQS = 1
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) (
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input wire clk,
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input wire reset,
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// inputs
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input wire req_valid,
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input wire [NUM_REQS-1:0] req_tmask,
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input wire [1:0][NUM_REQS-1:0][`TEX_FXD_BITS-1:0] req_coords,
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input wire [`TEX_FORMAT_BITS-1:0] req_format,
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input wire [`TEX_FILTER_BITS-1:0] req_filter,
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input wire [1:0][`TEX_WRAP_BITS-1:0] req_wraps,
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input wire [`TEX_ADDR_BITS-1:0] req_baseaddr,
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input wire [NUM_REQS-1:0][`TEX_MIPOFF_BITS-1:0] req_mipoff,
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input wire [NUM_REQS-1:0][1:0][`TEX_LOD_BITS-1:0] req_logdims,
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input wire [REQ_INFOW-1:0] req_info,
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output wire req_ready,
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// outputs
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output wire rsp_valid,
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output wire [NUM_REQS-1:0] rsp_tmask,
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output wire [`TEX_FILTER_BITS-1:0] rsp_filter,
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output wire [`TEX_LGSTRIDE_BITS-1:0] rsp_lgstride,
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output wire [NUM_REQS-1:0][3:0][31:0] rsp_addr,
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output wire [NUM_REQS-1:0][1:0][`TEX_BLEND_FRAC-1:0] rsp_blends,
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output wire [REQ_INFOW-1:0] rsp_info,
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input wire rsp_ready
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);
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`UNUSED_PARAM (CORE_ID)
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localparam SHIFT_BITS = $clog2(`TEX_FXD_FRAC+1);
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localparam PITCH_BITS = `MAX(`TEX_LOD_BITS, `TEX_LGSTRIDE_BITS) + 1;
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localparam SCALED_X_W = `TEX_DIM_BITS + `TEX_BLEND_FRAC;
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localparam OFFSET_U_W = `TEX_DIM_BITS + `TEX_LGSTRIDE_MAX;
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localparam OFFSET_V_W = `TEX_DIM_BITS + `TEX_DIM_BITS + `TEX_LGSTRIDE_MAX;
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wire valid_s0;
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wire [NUM_REQS-1:0] tmask_s0;
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wire [`TEX_FILTER_BITS-1:0] filter_s0;
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wire [REQ_INFOW-1:0] req_info_s0;
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wire [NUM_REQS-1:0][1:0][`TEX_FXD_FRAC-1:0] clamped_lo, clamped_lo_s0;
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wire [NUM_REQS-1:0][1:0][`TEX_FXD_FRAC-1:0] clamped_hi, clamped_hi_s0;
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wire [NUM_REQS-1:0][1:0][SHIFT_BITS-1:0] dim_shift, dim_shift_s0;
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wire [`TEX_LGSTRIDE_BITS-1:0] log_stride, log_stride_s0;
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wire [NUM_REQS-1:0][31:0] mip_addr, mip_addr_s0;
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wire [NUM_REQS-1:0][PITCH_BITS-1:0] log_pitch, log_pitch_s0;
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wire [NUM_REQS-1:0][PITCH_BITS-1:0] log_pitch, log_pitch_s0;
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wire stall_out;
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// stride
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VX_tex_stride #(
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.CORE_ID (CORE_ID)
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) tex_stride (
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.format (req_format),
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.log_stride (log_stride)
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);
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// addressing mode
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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for (genvar j = 0; j < 2; ++j) begin
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wire [`TEX_FXD_FRAC-1:0] delta = (`TEX_FXD_HALF >> req_logdims[i][j]);
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wire [`TEX_FXD_BITS-1:0] coord_lo = req_filter ? (req_coords[j][i] - `TEX_FXD_BITS'(delta)) : req_coords[j][i];
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wire [`TEX_FXD_BITS-1:0] coord_hi = req_filter ? (req_coords[j][i] + `TEX_FXD_BITS'(delta)) : req_coords[j][i];
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_lo (
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.wrap_i (req_wraps[j]),
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.coord_i (coord_lo),
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.coord_o (clamped_lo[i][j])
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);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_hi (
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.wrap_i (req_wraps[j]),
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.coord_i (coord_hi),
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.coord_o (clamped_hi[i][j])
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);
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assign dim_shift[i][j] = (`TEX_FXD_FRAC - `TEX_BLEND_FRAC - req_logdims[i][j]);
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end
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assign log_pitch[i] = PITCH_BITS'(req_logdims[i][0]) + PITCH_BITS'(log_stride);
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assign mip_addr[i] = req_baseaddr + 32'(req_mipoff[i]);
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end
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VX_pipe_register #(
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.DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_LGSTRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * SHIFT_BITS + 32 + 2 * 2 * `TEX_FXD_FRAC)),
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.RESETW (1)
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) pipe_reg0 (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({req_valid, req_tmask, req_filter, log_stride, req_info, log_pitch, dim_shift, mip_addr, clamped_lo, clamped_hi}),
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.data_out ({valid_s0, tmask_s0, filter_s0, log_stride_s0, req_info_s0, log_pitch_s0, dim_shift_s0, mip_addr_s0, clamped_lo_s0, clamped_hi_s0})
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);
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// addresses generation
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wire [NUM_REQS-1:0][1:0][SCALED_X_W-1:0] scaled_lo;
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wire [NUM_REQS-1:0][1:0][SCALED_X_W-1:0] scaled_hi;
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wire [NUM_REQS-1:0][OFFSET_U_W-1:0] offset_u_lo;
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wire [NUM_REQS-1:0][OFFSET_U_W-1:0] offset_u_hi;
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wire [NUM_REQS-1:0][OFFSET_V_W-1:0] offset_v_lo;
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wire [NUM_REQS-1:0][OFFSET_V_W-1:0] offset_v_hi;
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wire [NUM_REQS-1:0][31:0] base_addr_lo;
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wire [NUM_REQS-1:0][31:0] base_addr_hi;
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wire [NUM_REQS-1:0][1:0][`TEX_BLEND_FRAC-1:0] blends;
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wire [NUM_REQS-1:0][3:0][31:0] addr;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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for (genvar j = 0; j < 2; ++j) begin
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assign scaled_lo[i][j] = SCALED_X_W'(clamped_lo_s0[i][j] >> dim_shift_s0[i][j]);
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assign scaled_hi[i][j] = SCALED_X_W'(clamped_hi_s0[i][j] >> dim_shift_s0[i][j]);
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assign blends[i][j] = filter_s0 ? scaled_lo[i][j][`TEX_BLEND_FRAC-1:0] : `TEX_BLEND_FRAC'(0);
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end
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end
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign offset_u_lo[i] = OFFSET_U_W'(scaled_lo[i][0][`TEX_BLEND_FRAC +: `TEX_DIM_BITS]) << log_stride_s0;
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assign offset_u_hi[i] = OFFSET_U_W'(scaled_hi[i][0][`TEX_BLEND_FRAC +: `TEX_DIM_BITS]) << log_stride_s0;
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assign offset_v_lo[i] = OFFSET_V_W'(scaled_lo[i][1][`TEX_BLEND_FRAC +: `TEX_DIM_BITS]) << log_pitch_s0[i];
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assign offset_v_hi[i] = OFFSET_V_W'(scaled_hi[i][1][`TEX_BLEND_FRAC +: `TEX_DIM_BITS]) << log_pitch_s0[i];
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assign base_addr_lo[i] = mip_addr_s0[i] + 32'(offset_v_lo[i]);
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assign base_addr_hi[i] = mip_addr_s0[i] + 32'(offset_v_hi[i]);
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assign addr[i][0] = base_addr_lo[i] + 32'(offset_u_lo[i]);
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assign addr[i][1] = base_addr_lo[i] + 32'(offset_u_hi[i]);
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assign addr[i][2] = base_addr_hi[i] + 32'(offset_u_lo[i]);
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assign addr[i][3] = base_addr_hi[i] + 32'(offset_u_hi[i]);
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end
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assign stall_out = rsp_valid && ~rsp_ready;
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VX_pipe_register #(
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.DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_LGSTRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `TEX_BLEND_FRAC) + REQ_INFOW),
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.RESETW (1)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({valid_s0, tmask_s0, filter_s0, log_stride_s0, addr, blends, req_info_s0}),
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.data_out ({rsp_valid, rsp_tmask, rsp_filter, rsp_lgstride, rsp_addr, rsp_blends, rsp_info})
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);
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assign req_ready = ~stall_out;
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`ifdef DBG_TRACE_TEX
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wire [`NW_BITS-1:0] rsp_wid;
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wire [31:0] rsp_PC;
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assign {rsp_wid, rsp_PC} = rsp_info[`NW_BITS+32-1:0];
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always @(posedge clk) begin
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if (req_valid && ~stall_out) begin
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dpi_trace("%d: *** log_pitch=", $time);
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`TRACE_ARRAY1D(log_pitch, NUM_REQS);
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dpi_trace(", mip_addr=");
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`TRACE_ARRAY1D(mip_addr, NUM_REQS);
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dpi_trace(", req_logdims=");
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`TRACE_ARRAY2D(req_logdims, 2, NUM_REQS);
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dpi_trace(", clamped_lo=");
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`TRACE_ARRAY2D(clamped_lo, 2, NUM_REQS);
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dpi_trace(", clamped_hi=");
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`TRACE_ARRAY2D(clamped_hi, 2, NUM_REQS);
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dpi_trace("\n");
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end
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if (valid_s0 && ~stall_out) begin
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dpi_trace("%d: *** scaled_lo=", $time);
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`TRACE_ARRAY2D(scaled_lo, 2, NUM_REQS);
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dpi_trace(", scaled_hi=");
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`TRACE_ARRAY2D(scaled_hi, 2, NUM_REQS);
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dpi_trace(", offset_u_lo=");
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`TRACE_ARRAY1D(offset_u_lo, NUM_REQS);
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dpi_trace(", offset_u_hi=");
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`TRACE_ARRAY1D(offset_u_hi, NUM_REQS);
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dpi_trace(", offset_v_lo=");
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`TRACE_ARRAY1D(offset_v_lo, NUM_REQS);
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dpi_trace(", offset_v_hi=");
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`TRACE_ARRAY1D(offset_v_hi, NUM_REQS);
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dpi_trace(", base_addr_lo=");
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`TRACE_ARRAY1D(base_addr_lo, NUM_REQS);
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dpi_trace(", base_addr_hi=");
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`TRACE_ARRAY1D(base_addr_hi, NUM_REQS);
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dpi_trace("\n");
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end
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if (rsp_valid && rsp_ready) begin
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dpi_trace("%d: core%0d-tex-addr: wid=%0d, PC=%0h, tmask=%b, req_filter=%0d, lgstride=%0d, addr=",
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$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask, rsp_filter, rsp_lgstride);
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`TRACE_ARRAY2D(rsp_addr, 4, NUM_REQS);
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dpi_trace("\n");
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end
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end
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`endif
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endmodule |