22 lines
536 B
Verilog
22 lines
536 B
Verilog
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`ifndef VX_LSU_REQ_INTER
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`define VX_LSU_REQ_INTER
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`include "VX_define.vh"
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interface VX_lsu_req_if ();
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wire [`NUM_THREADS-1:0] valid;
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wire [31:0] lsu_pc;
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wire [`NW_BITS-1:0] warp_num;
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wire [`NUM_THREADS-1:0][31:0] store_data;
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wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data
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wire [31:0] offset; // itype_immed
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wire [2:0] mem_read;
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wire [2:0] mem_write;
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wire [4:0] rd;
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wire [1:0] wb;
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endinterface
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`endif |