276 lines
11 KiB
Verilog
276 lines
11 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_shared_mem #(
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parameter CACHE_ID = 0,
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// Size of cache in bytes
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parameter CACHE_SIZE = 16384,
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// Number of banks
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parameter NUM_BANKS = 4,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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// Number of Word requests per cycle
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parameter NUM_REQS = NUM_BANKS,
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// Core Request Queue Size
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parameter CREQ_SIZE = 4,
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// core request tag size
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parameter CORE_TAG_WIDTH = 1,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = 0,
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// bank offset from beginning of index range
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parameter BANK_ADDR_OFFSET = 0
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) (
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input wire clk,
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input wire reset,
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// PERF
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_cache_if,
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`endif
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// Core request
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input wire [NUM_REQS-1:0] core_req_valid,
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input wire [NUM_REQS-1:0] core_req_rw,
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input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
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input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
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input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data,
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input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
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output wire [NUM_REQS-1:0] core_req_ready,
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// Core response
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output wire [NUM_REQS-1:0] core_rsp_valid,
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output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
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output wire [CORE_TAG_WIDTH-1:0] core_rsp_tag,
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input wire core_rsp_ready
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);
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`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value"))
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`UNUSED_PARAM (CACHE_ID)
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`UNUSED_PARAM (CORE_TAG_ID_BITS)
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localparam CACHE_LINE_SIZE = WORD_SIZE;
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`ifdef DBG_CACHE_REQ_INFO
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/* verilator lint_off UNUSED */
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wire [31:0] debug_pc_st0;
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wire [`NW_BITS-1:0] debug_wid_st0;
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/* verilator lint_on UNUSED */
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`endif
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wire [NUM_BANKS-1:0] per_bank_core_req_valid_unqual;
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wire [NUM_BANKS-1:0] per_bank_core_req_rw_unqual;
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wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr_unqual;
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wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen_unqual;
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wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_unqual;
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wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_unqual;
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wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_unqual;
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wire per_bank_core_req_ready_unqual;
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VX_cache_core_req_bank_sel #(
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.CACHE_LINE_SIZE (WORD_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.NUM_PORTS (1),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.BANK_ADDR_OFFSET(BANK_ADDR_OFFSET),
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.SHARED_BANK_READY(1)
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) core_req_bank_sel (
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.clk (clk),
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.reset (reset),
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`ifdef PERF_ENABLE
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.bank_stalls(perf_cache_if.bank_stalls),
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`endif
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.core_req_valid (core_req_valid),
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.core_req_rw (core_req_rw),
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.core_req_addr (core_req_addr),
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.core_req_byteen(core_req_byteen),
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.core_req_data (core_req_data),
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.core_req_tag (core_req_tag),
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.core_req_ready (core_req_ready),
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.per_bank_core_req_valid (per_bank_core_req_valid_unqual),
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.per_bank_core_req_tid (per_bank_core_req_tid_unqual),
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.per_bank_core_req_rw (per_bank_core_req_rw_unqual),
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.per_bank_core_req_addr (per_bank_core_req_addr_unqual),
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`UNUSED_PIN (per_bank_core_req_wsel),
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.per_bank_core_req_byteen(per_bank_core_req_byteen_unqual),
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.per_bank_core_req_tag (per_bank_core_req_tag_unqual),
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.per_bank_core_req_data (per_bank_core_req_data_unqual),
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.per_bank_core_req_ready (per_bank_core_req_ready_unqual)
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);
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wire [NUM_BANKS-1:0] per_bank_core_req_valid;
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wire [NUM_BANKS-1:0] per_bank_core_req_rw;
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wire [NUM_BANKS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr;
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wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen;
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wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data;
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wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag;
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wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid;
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wire creq_push, creq_pop, creq_empty, creq_full;
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wire crsq_in_ready;
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assign creq_push = (| core_req_valid) && !creq_full;
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assign creq_pop = ~creq_empty && crsq_in_ready;
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assign per_bank_core_req_ready_unqual = ~creq_full;
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wire [NUM_REQS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr_qual;
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`UNUSED_VAR (per_bank_core_req_addr_unqual)
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign per_bank_core_req_addr_qual[i] = per_bank_core_req_addr_unqual[i][`LINE_SELECT_BITS-1:0];
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end
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VX_fifo_queue #(
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.DATAW (NUM_BANKS * (1 + 1 + `LINE_SELECT_BITS + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS)),
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.SIZE (CREQ_SIZE),
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.BUFFERED (1)
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) core_req_queue (
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.clk (clk),
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.reset (reset),
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.push (creq_push),
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.pop (creq_pop),
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.data_in ({per_bank_core_req_valid_unqual,
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per_bank_core_req_rw_unqual,
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per_bank_core_req_addr_qual,
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per_bank_core_req_byteen_unqual,
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per_bank_core_req_data_unqual,
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per_bank_core_req_tag_unqual,
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per_bank_core_req_tid_unqual}),
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.data_out({per_bank_core_req_valid,
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per_bank_core_req_rw,
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per_bank_core_req_addr,
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per_bank_core_req_byteen,
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per_bank_core_req_data,
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per_bank_core_req_tag,
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per_bank_core_req_tid}),
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.empty (creq_empty),
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.full (creq_full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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);
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wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data;
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for (genvar i = 0; i < NUM_BANKS; i++) begin
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VX_sp_ram #(
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.DATAW (`WORD_WIDTH),
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.SIZE (`LINES_PER_BANK),
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.BYTEENW (WORD_SIZE),
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.RWCHECK (1)
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) data (
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.clk (clk),
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.addr (per_bank_core_req_addr[i]),
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.wren (per_bank_core_req_valid[i] && per_bank_core_req_rw[i]),
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.byteen (per_bank_core_req_byteen[i]),
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.rden (1'b1),
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.din (per_bank_core_req_data[i]),
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.dout (per_bank_core_rsp_data[i])
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);
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end
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reg [NUM_REQS-1:0] core_rsp_valids_in;
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reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_in;
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reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_in;
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always @(*) begin
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core_rsp_valids_in = 0;
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core_rsp_data_in = 'x;
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core_rsp_tag_in = 'x;
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for (integer i = 0; i < NUM_BANKS; i++) begin
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if (per_bank_core_req_valid[i]) begin
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core_rsp_valids_in[per_bank_core_req_tid[i]] = 1;
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core_rsp_data_in[per_bank_core_req_tid[i]] = per_bank_core_rsp_data[i];
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core_rsp_tag_in = per_bank_core_req_tag[i];
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end
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end
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end
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`ifdef DBG_CACHE_REQ_INFO
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if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
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assign {debug_pc_st0, debug_wid_st0} = core_rsp_tag_in[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
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end else begin
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assign {debug_pc_st0, debug_wid_st0} = 0;
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end
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`endif
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wire [NUM_REQS-1:0] core_rsp_valids_out;
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wire core_rsp_valid_out;
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wire core_rsp_rw = | (per_bank_core_req_valid & per_bank_core_req_rw);
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wire crsq_in_valid = ~creq_empty && ~core_rsp_rw;
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VX_skid_buffer #(
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.DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH)
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) core_rsp_req (
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.clk (clk),
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.reset (reset),
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.valid_in (crsq_in_valid),
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.data_in ({core_rsp_valids_in, core_rsp_data_in, core_rsp_tag_in}),
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.ready_in (crsq_in_ready),
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.valid_out (core_rsp_valid_out),
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.data_out ({core_rsp_valids_out, core_rsp_data, core_rsp_tag}),
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.ready_out (core_rsp_ready)
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);
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assign core_rsp_valid = core_rsp_valids_out & {NUM_REQS{core_rsp_valid_out}};
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`ifdef DBG_PRINT_CACHE_BANK
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always @(posedge clk) begin
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if (!crsq_in_ready) begin
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$display("%t: cache%0d pipeline-stall", $time, CACHE_ID);
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end
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if (creq_pop) begin
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if (core_rsp_rw)
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$display("%t: cache%0d core-wr-req: tmask=%0b, addr=%0h, tag=%0h, byteen=%b, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, per_bank_core_req_valid, per_bank_core_req_addr, per_bank_core_req_tag, per_bank_core_req_byteen, per_bank_core_req_data, debug_wid_st0, debug_pc_st0);
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else
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$display("%t: cache%0d core-rd-req: tmask=%0b, addr=%0h, tag=%0h, byteen=%b, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, per_bank_core_req_valid, per_bank_core_req_addr, per_bank_core_req_tag, per_bank_core_req_byteen, per_bank_core_rsp_data, debug_wid_st0, debug_pc_st0);
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end
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end
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`endif
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`ifdef PERF_ENABLE
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// per cycle: core_reads, core_writes
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reg [($clog2(NUM_REQS+1)-1):0] perf_core_reads_per_cycle, perf_core_writes_per_cycle;
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reg [($clog2(NUM_REQS+1)-1):0] perf_crsp_stall_per_cycle;
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assign perf_core_reads_per_cycle = $countones(core_req_valid & core_req_ready & ~core_req_rw);
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assign perf_core_writes_per_cycle = $countones(core_req_valid & core_req_ready & core_req_rw);
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if (CORE_TAG_ID_BITS != 0) begin
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assign perf_crsp_stall_per_cycle = $countones(core_rsp_valid & {NUM_REQS{!core_rsp_ready}});
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end else begin
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assign perf_crsp_stall_per_cycle = $countones(core_rsp_valid & ~core_rsp_ready);
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end
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reg [43:0] perf_core_reads;
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reg [43:0] perf_core_writes;
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reg [43:0] perf_crsp_stalls;
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always @(posedge clk) begin
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if (reset) begin
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perf_core_reads <= 0;
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perf_core_writes <= 0;
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perf_crsp_stalls <= 0;
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end else begin
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perf_core_reads <= perf_core_reads + 44'(perf_core_reads_per_cycle);
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perf_core_writes <= perf_core_writes + 44'(perf_core_writes_per_cycle);
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perf_crsp_stalls <= perf_crsp_stalls + 44'(perf_crsp_stall_per_cycle);
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end
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end
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assign perf_cache_if.reads = perf_core_reads;
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assign perf_cache_if.writes = perf_core_writes;
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assign perf_cache_if.read_misses = '0;
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assign perf_cache_if.write_misses = '0;
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assign perf_cache_if.pipe_stalls = '0;
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assign perf_cache_if.crsp_stalls = perf_crsp_stalls;
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`endif
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endmodule |