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vortex/rtl
History
Savan Roshan 3a71a2ebdb Fixed bugs in parameterization
2019-11-06 01:09:30 -05:00
..
cache
Fixed bugs in parameterization
2019-11-06 01:09:30 -05:00
interfaces
Fixed bugs in parameterization
2019-11-06 01:09:30 -05:00
modelsim
Added prefix DCACHE_
2019-11-05 08:33:38 -05:00
pipe_regs
Modelsim basic sim
2019-10-26 00:34:57 -04:00
quartus
Full Evaluation Attempt 1
2019-09-11 01:39:00 -04:00
shared_memory
Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data
2019-10-28 15:06:23 -04:00
simulate
Added prefix DCACHE_
2019-11-05 08:33:38 -05:00
.DS_Store
New RF with Evaluation
2019-09-11 01:04:23 -04:00
byte_enabled_simple_dual_port_ram.v
Synthesis Cleanup 1
2019-10-28 13:43:12 -04:00
Makefile
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00
results.txt
CACHE FINALLY WORKING
2019-10-25 04:01:23 -04:00
Vortex.v
Added prefix DCACHE_
2019-11-05 08:33:38 -05:00
VX_alu.v
Removed dependancy on
2019-10-27 22:30:32 -04:00
VX_back_end.v
GPR ASIC Working
2019-10-29 23:20:16 -04:00
VX_countones.v
Modelsim Makefile compile + simulate - DPI
2019-10-26 19:01:49 -04:00
VX_csr_handler.v
New Warp Scheduler + VCD Enable
2019-09-15 00:12:41 -04:00
VX_csr_wrapper.v
Removed dependancy on
2019-10-27 22:30:32 -04:00
VX_decode.v
Modelsim Working + Simulating + dumping - Some bugs
2019-10-27 03:36:02 -04:00
VX_define.v
Fixed bugs in parameterization
2019-11-06 01:09:30 -05:00
VX_dmem_controller.v
Added Parameterization
2019-11-04 13:20:34 -05:00
VX_execute_unit.v
Intrinsics: tests for TMC+Control Divergence
2019-11-01 21:53:37 -04:00
VX_fetch.v
Intrinsics: tests for TMC+Control Divergence
2019-11-01 21:53:37 -04:00
VX_front_end.v
FIxed first circular issue
2019-10-24 10:38:04 -04:00
VX_generic_priority_encoder.v
Finished cache not tested
2019-10-23 19:07:26 -04:00
VX_generic_register.v
reset posedge
2019-10-21 11:34:12 -04:00
VX_generic_stack.v
Readded IPDOM stack + SPLIT/Join tested
2019-10-21 21:24:49 -04:00
VX_gpgpu_inst.v
Intrinsics: tests for TMC+Control Divergence
2019-11-01 21:53:37 -04:00
VX_gpr_stage.v
GPR ASIC Working
2019-10-29 23:20:16 -04:00
VX_gpr_wrapper.v
Fixed ASIC GPR warp number delay
2019-11-03 15:56:18 -05:00
VX_gpr.v
Fixed ASIC GPR warp number delay
2019-11-03 15:56:18 -05:00
VX_inst_multiplex.v
Modelsim basic sim
2019-10-26 00:34:57 -04:00
VX_lsu_addr_gen.v
Modelsim basic sim
2019-10-26 00:34:57 -04:00
VX_lsu.v
wsapwn tested - NOTE in vx_main.c
2019-11-03 20:56:07 -05:00
VX_priority_encoder_w_mask.v
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00
VX_priority_encoder.v
Modelsim basic sim
2019-10-26 00:34:57 -04:00
VX_scheduler.v
Fixed ASIC GPR warp number delay
2019-11-03 15:56:18 -05:00
VX_warp_scheduler.v
wsapwn tested - NOTE in vx_main.c
2019-11-03 20:56:07 -05:00
VX_warp.v
Modelsim Working + Simulating + dumping - Some bugs
2019-10-27 03:36:02 -04:00
VX_writeback.v
Modelsim basic sim
2019-10-26 00:34:57 -04:00