161 lines
4.9 KiB
Verilog
161 lines
4.9 KiB
Verilog
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`include "VX_define.v"
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module VX_forwarding (
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// INFO FROM DECODE
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input wire[4:0] in_decode_src1,
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input wire[4:0] in_decode_src2,
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input wire[11:0] in_decode_csr_address,
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// INFO FROM EXE
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input wire[4:0] in_execute_dest,
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input wire[1:0] in_execute_wb,
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input wire[31:0] in_execute_alu_result,
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input wire[31:0] in_execute_PC_next,
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input wire in_execute_is_csr,
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input wire[11:0] in_execute_csr_address,
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// INFO FROM MEM
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input wire[4:0] in_memory_dest,
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input wire[1:0] in_memory_wb,
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input wire[31:0] in_memory_alu_result,
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input wire[31:0] in_memory_mem_data,
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input wire[31:0] in_memory_PC_next,
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input wire in_memory_is_csr,
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input wire[11:0] in_memory_csr_address,
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input wire[31:0] in_memory_csr_result,
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// INFO FROM WB
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input wire[4:0] in_writeback_dest,
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input wire[1:0] in_writeback_wb,
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input wire[31:0] in_writeback_alu_result,
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input wire[31:0] in_writeback_mem_data,
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input wire[31:0] in_writeback_PC_next,
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// OUT SIGNALS
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output wire out_src1_fwd,
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output wire out_src2_fwd,
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output wire out_csr_fwd,
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output wire[31:0] out_src1_fwd_data,
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output wire[31:0] out_src2_fwd_data,
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output wire[31:0] out_csr_fwd_data,
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output wire out_fwd_stall
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);
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wire exe_mem_read;
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wire mem_mem_read;
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wire wb_mem_read ;
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wire exe_jal;
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wire mem_jal;
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wire wb_jal ;
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wire exe_csr;
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wire mem_csr;
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wire src1_exe_fwd;
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wire src1_mem_fwd;
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wire src1_wb_fwd;
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wire src2_exe_fwd;
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wire src2_mem_fwd;
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wire src2_wb_fwd;
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wire csr_exe_fwd;
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wire csr_mem_fwd;
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assign exe_mem_read = (in_execute_wb == `WB_MEM);
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assign mem_mem_read = (in_memory_wb == `WB_MEM);
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assign wb_mem_read = (in_writeback_wb == `WB_MEM);
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assign exe_jal = (in_execute_wb == `WB_JAL);
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assign mem_jal = (in_memory_wb == `WB_JAL);
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assign wb_jal = (in_writeback_wb == `WB_JAL);
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assign exe_csr = (in_execute_is_csr == 1'b1);
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assign mem_csr = (in_memory_is_csr == 1'b1);
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// SRC1
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assign src1_exe_fwd = ((in_decode_src1 == in_execute_dest) &&
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(in_decode_src1 != `ZERO_REG) &&
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(in_execute_wb != `NO_WB));
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assign src1_mem_fwd = ((in_decode_src1 == in_memory_dest) &&
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(in_decode_src1 != `ZERO_REG) &&
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(in_memory_wb != `NO_WB) &&
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(!src1_exe_fwd));
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assign src1_wb_fwd = ((in_decode_src1 == in_writeback_dest) &&
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(in_decode_src1 != `ZERO_REG) &&
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(in_writeback_wb != `NO_WB) &&
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(!src1_exe_fwd) &&
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(!src1_mem_fwd));
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assign out_src1_fwd = src1_exe_fwd || src1_mem_fwd || src1_wb_fwd; // COMMENT
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// SRC2
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assign src2_exe_fwd = ((in_decode_src2 == in_execute_dest) &&
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(in_decode_src2 != `ZERO_REG) &&
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(in_execute_wb != `NO_WB));
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assign src2_mem_fwd = ((in_decode_src2 == in_memory_dest) &&
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(in_decode_src2 != `ZERO_REG) &&
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(in_memory_wb != `NO_WB) &&
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(!src2_exe_fwd));
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assign src2_wb_fwd = ((in_decode_src2 == in_writeback_dest) &&
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(in_decode_src2 != `ZERO_REG) &&
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(in_writeback_wb != `NO_WB) &&
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(!src2_exe_fwd) &&
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(!src2_mem_fwd));
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assign out_src2_fwd = src2_exe_fwd || src2_mem_fwd || src2_wb_fwd; // COMMENT
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// CSR
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assign csr_exe_fwd = (in_decode_csr_address == in_execute_csr_address) && exe_csr;
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assign csr_mem_fwd = (in_decode_csr_address == in_memory_csr_address) && mem_csr && !csr_exe_fwd;
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assign out_csr_fwd = csr_exe_fwd || csr_mem_fwd; // COMMENT
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wire exe_mem_read_stall = ((src1_exe_fwd || src2_exe_fwd) && exe_mem_read) ? `STALL : `NO_STALL;
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wire mem_mem_read_stall = ((src1_mem_fwd || src2_mem_fwd) && mem_mem_read) ? `STALL : `NO_STALL;
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assign out_fwd_stall = exe_mem_read_stall || mem_mem_read_stall;
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// always @(*) begin
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// if (out_fwd_stall) $display("FWD STALL");
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// end
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assign out_src1_fwd_data = src1_exe_fwd ? ((exe_jal) ? in_execute_PC_next : in_execute_alu_result) :
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(src1_mem_fwd) ? ((mem_jal) ? in_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) :
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( src1_wb_fwd ) ? (wb_jal ? in_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) :
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32'hdeadbeef; // COMMENT
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assign out_src2_fwd_data = src2_exe_fwd ? ((exe_jal) ? in_execute_PC_next : in_execute_alu_result) :
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(src2_mem_fwd) ? ((mem_jal) ? in_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) :
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( src2_wb_fwd ) ? (wb_jal ? in_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) :
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32'hdeadbeef; // COMMENT
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assign out_csr_fwd_data = csr_exe_fwd ? in_execute_alu_result :
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csr_mem_fwd ? in_memory_csr_result :
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32'hdeadbeef; // COMMENT
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endmodule // VX_forwarding
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