c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
495 lines
20 KiB
Systemverilog
495 lines
20 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_cache_define.vh"
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module VX_cache_wrap import VX_gpu_pkg::*; #(
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parameter `STRING INSTANCE_ID = "",
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// Number of Word requests per cycle
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parameter NUM_REQS = 4,
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// Size of cache in bytes
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parameter CACHE_SIZE = 4096,
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// Size of line inside a bank in bytes
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parameter LINE_SIZE = 64,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Number of associative ways
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parameter NUM_WAYS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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// Core Response Queue Size
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parameter CRSQ_SIZE = 2,
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// Miss Reserv Queue Knob
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parameter MSHR_SIZE = 8,
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// Memory Response Queue Size
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parameter MRSQ_SIZE = 0,
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// Memory Request Queue Size
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parameter MREQ_SIZE = 4,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Request debug identifier
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parameter UUID_WIDTH = 0,
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// core request tag size
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parameter TAG_WIDTH = UUID_WIDTH + 1,
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// enable bypass for non-cacheable addresses
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parameter NC_TAG_BIT = 0,
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parameter NC_ENABLE = 0,
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// Force bypass for all requests
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parameter PASSTHRU = 0,
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// Core response output register
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parameter CORE_OUT_REG = 0,
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// Memory request output register
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parameter MEM_OUT_REG = 0
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) (
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input wire clk,
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input wire reset,
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// PERF
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`ifdef PERF_ENABLE
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output cache_perf_t cache_perf,
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`endif
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VX_mem_bus_if.slave core_bus_if [NUM_REQS],
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VX_mem_bus_if.master mem_bus_if
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);
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`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid parameter: NUM_BANKS=%d, NUM_REQS=%d", NUM_BANKS, NUM_REQS))
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`STATIC_ASSERT(NUM_BANKS == (1 << `CLOG2(NUM_BANKS)), ("invalid parameter"))
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localparam MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE);
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localparam CORE_TAG_X_WIDTH = TAG_WIDTH - NC_ENABLE;
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localparam MEM_TAG_X_WIDTH = MSHR_ADDR_WIDTH + `CS_BANK_SEL_BITS;
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localparam MEM_TAG_WIDTH = PASSTHRU ? (NC_ENABLE ? `CACHE_NC_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, TAG_WIDTH) :
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`CACHE_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, TAG_WIDTH)) :
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(NC_ENABLE ? `CACHE_NC_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS, NUM_REQS, LINE_SIZE, WORD_SIZE, TAG_WIDTH) :
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`CACHE_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS));
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localparam NC_BYPASS = (NC_ENABLE || PASSTHRU);
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localparam DIRECT_PASSTHRU = PASSTHRU && (`CS_WORD_SEL_BITS == 0) && (NUM_REQS == 1);
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wire [NUM_REQS-1:0] core_req_valid;
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wire [NUM_REQS-1:0] core_req_rw;
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wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr;
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wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen;
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wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data;
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wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_req_tag;
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wire [NUM_REQS-1:0] core_req_ready;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_req_valid[i] = core_bus_if[i].req_valid;
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assign core_req_rw[i] = core_bus_if[i].req_data.rw;
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assign core_req_addr[i] = core_bus_if[i].req_data.addr;
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assign core_req_byteen[i] = core_bus_if[i].req_data.byteen;
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assign core_req_data[i] = core_bus_if[i].req_data.data;
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assign core_req_tag[i] = core_bus_if[i].req_data.tag;
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assign core_bus_if[i].req_ready = core_req_ready[i];
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end
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///////////////////////////////////////////////////////////////////////////
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// Core response buffering
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wire [NUM_REQS-1:0] core_rsp_valid_s;
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wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data_s;
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wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s;
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wire [NUM_REQS-1:0] core_rsp_ready_s;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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`RESET_RELAY (core_rsp_reset, reset);
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VX_elastic_buffer #(
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.DATAW (`CS_WORD_WIDTH + TAG_WIDTH),
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.SIZE ((NC_BYPASS && !DIRECT_PASSTHRU) ? `OUT_REG_TO_EB_SIZE(CORE_OUT_REG) : 0),
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.OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG))
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) core_rsp_buf (
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.clk (clk),
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.reset (core_rsp_reset),
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.valid_in (core_rsp_valid_s[i]),
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.ready_in (core_rsp_ready_s[i]),
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.data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}),
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.data_out ({core_bus_if[i].rsp_data.data, core_bus_if[i].rsp_data.tag}),
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.valid_out (core_bus_if[i].rsp_valid),
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.ready_out (core_bus_if[i].rsp_ready)
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);
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end
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///////////////////////////////////////////////////////////////////////////
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// Memory request buffering
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wire mem_req_valid_s;
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wire mem_req_rw_s;
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wire [LINE_SIZE-1:0] mem_req_byteen_s;
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wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr_s;
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wire [`CS_LINE_WIDTH-1:0] mem_req_data_s;
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wire [MEM_TAG_WIDTH-1:0] mem_req_tag_s;
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wire mem_req_ready_s;
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VX_elastic_buffer #(
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.DATAW (1 + LINE_SIZE + `CS_MEM_ADDR_WIDTH + `CS_LINE_WIDTH + MEM_TAG_WIDTH),
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.SIZE ((NC_BYPASS && !DIRECT_PASSTHRU) ? `OUT_REG_TO_EB_SIZE(MEM_OUT_REG) : 0),
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.OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG))
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) mem_req_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (mem_req_valid_s),
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.ready_in (mem_req_ready_s),
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.data_in ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}),
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.data_out ({mem_bus_if.req_data.rw, mem_bus_if.req_data.byteen, mem_bus_if.req_data.addr, mem_bus_if.req_data.data, mem_bus_if.req_data.tag}),
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.valid_out (mem_bus_if.req_valid),
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.ready_out (mem_bus_if.req_ready)
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);
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///////////////////////////////////////////////////////////////////////////
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// Core request
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wire [NUM_REQS-1:0] core_req_valid_b;
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wire [NUM_REQS-1:0] core_req_rw_b;
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wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr_b;
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wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen_b;
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wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data_b;
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wire [NUM_REQS-1:0][CORE_TAG_X_WIDTH-1:0] core_req_tag_b;
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wire [NUM_REQS-1:0] core_req_ready_b;
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// Core response
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wire [NUM_REQS-1:0] core_rsp_valid_b;
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wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data_b;
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wire [NUM_REQS-1:0][CORE_TAG_X_WIDTH-1:0] core_rsp_tag_b;
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wire [NUM_REQS-1:0] core_rsp_ready_b;
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// Memory request
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wire mem_req_valid_b;
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wire mem_req_rw_b;
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wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr_b;
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wire [LINE_SIZE-1:0] mem_req_byteen_b;
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wire [`CS_LINE_WIDTH-1:0] mem_req_data_b;
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wire [MEM_TAG_X_WIDTH-1:0] mem_req_tag_b;
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wire mem_req_ready_b;
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// Memory response
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wire mem_rsp_valid_b;
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wire [`CS_LINE_WIDTH-1:0] mem_rsp_data_b;
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wire [MEM_TAG_X_WIDTH-1:0] mem_rsp_tag_b;
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wire mem_rsp_ready_b;
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if (NC_BYPASS) begin
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`RESET_RELAY (nc_bypass_reset, reset);
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VX_cache_bypass #(
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.NUM_REQS (NUM_REQS),
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.NC_TAG_BIT (NC_TAG_BIT),
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.NC_ENABLE (NC_ENABLE),
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.PASSTHRU (PASSTHRU),
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.CORE_ADDR_WIDTH (`CS_WORD_ADDR_WIDTH),
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.CORE_DATA_SIZE (WORD_SIZE),
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.CORE_TAG_IN_WIDTH (TAG_WIDTH),
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.MEM_ADDR_WIDTH (`CS_MEM_ADDR_WIDTH),
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.MEM_DATA_SIZE (LINE_SIZE),
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.MEM_TAG_IN_WIDTH (MEM_TAG_X_WIDTH),
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.MEM_TAG_OUT_WIDTH (MEM_TAG_WIDTH),
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.UUID_WIDTH (UUID_WIDTH)
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) cache_bypass (
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.clk (clk),
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.reset (nc_bypass_reset),
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// Core request in
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.core_req_valid_in (core_req_valid),
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.core_req_rw_in (core_req_rw),
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.core_req_byteen_in (core_req_byteen),
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.core_req_addr_in (core_req_addr),
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.core_req_data_in (core_req_data),
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.core_req_tag_in (core_req_tag),
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.core_req_ready_in (core_req_ready),
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// Core request out
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.core_req_valid_out (core_req_valid_b),
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.core_req_rw_out (core_req_rw_b),
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.core_req_byteen_out(core_req_byteen_b),
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.core_req_addr_out (core_req_addr_b),
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.core_req_data_out (core_req_data_b),
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.core_req_tag_out (core_req_tag_b),
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.core_req_ready_out (core_req_ready_b),
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// Core response in
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.core_rsp_valid_in (core_rsp_valid_b),
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.core_rsp_data_in (core_rsp_data_b),
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.core_rsp_tag_in (core_rsp_tag_b),
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.core_rsp_ready_in (core_rsp_ready_b),
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// Core response out
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.core_rsp_valid_out (core_rsp_valid_s),
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.core_rsp_data_out (core_rsp_data_s),
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.core_rsp_tag_out (core_rsp_tag_s),
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.core_rsp_ready_out (core_rsp_ready_s),
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// Memory request in
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.mem_req_valid_in (mem_req_valid_b),
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.mem_req_rw_in (mem_req_rw_b),
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.mem_req_addr_in (mem_req_addr_b),
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.mem_req_byteen_in (mem_req_byteen_b),
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.mem_req_data_in (mem_req_data_b),
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.mem_req_tag_in (mem_req_tag_b),
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.mem_req_ready_in (mem_req_ready_b),
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// Memory request out
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.mem_req_valid_out (mem_req_valid_s),
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.mem_req_addr_out (mem_req_addr_s),
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.mem_req_rw_out (mem_req_rw_s),
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.mem_req_byteen_out (mem_req_byteen_s),
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.mem_req_data_out (mem_req_data_s),
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.mem_req_tag_out (mem_req_tag_s),
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.mem_req_ready_out (mem_req_ready_s),
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// Memory response in
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.mem_rsp_valid_in (mem_bus_if.rsp_valid),
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.mem_rsp_data_in (mem_bus_if.rsp_data.data),
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.mem_rsp_tag_in (mem_bus_if.rsp_data.tag),
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.mem_rsp_ready_in (mem_bus_if.rsp_ready),
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// Memory response out
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.mem_rsp_valid_out (mem_rsp_valid_b),
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.mem_rsp_data_out (mem_rsp_data_b),
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.mem_rsp_tag_out (mem_rsp_tag_b),
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.mem_rsp_ready_out (mem_rsp_ready_b)
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);
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end else begin
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assign core_req_valid_b = core_req_valid;
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assign core_req_rw_b = core_req_rw;
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assign core_req_addr_b = core_req_addr;
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assign core_req_byteen_b= core_req_byteen;
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assign core_req_data_b = core_req_data;
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assign core_req_tag_b = core_req_tag;
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assign core_req_ready = core_req_ready_b;
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assign core_rsp_valid_s = core_rsp_valid_b;
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assign core_rsp_data_s = core_rsp_data_b;
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assign core_rsp_tag_s = core_rsp_tag_b;
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assign core_rsp_ready_b = core_rsp_ready_s;
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assign mem_req_valid_s = mem_req_valid_b;
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assign mem_req_addr_s = mem_req_addr_b;
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assign mem_req_rw_s = mem_req_rw_b;
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assign mem_req_byteen_s = mem_req_byteen_b;
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assign mem_req_data_s = mem_req_data_b;
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assign mem_req_ready_b = mem_req_ready_s;
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// Add explicit NC=0 flag to the memory request tag
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VX_bits_insert #(
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.N (MEM_TAG_WIDTH-1),
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.POS (NC_TAG_BIT)
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) mem_req_tag_insert (
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.data_in (mem_req_tag_b),
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.sel_in (1'b0),
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.data_out (mem_req_tag_s)
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);
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assign mem_rsp_valid_b = mem_bus_if.rsp_valid;
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assign mem_rsp_data_b = mem_bus_if.rsp_data.data;
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assign mem_bus_if.rsp_ready = mem_rsp_ready_b;
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// Remove NC flag from the memory response tag
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VX_bits_remove #(
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.N (MEM_TAG_WIDTH),
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.POS (NC_TAG_BIT)
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) mem_rsp_tag_remove (
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.data_in (mem_bus_if.rsp_data.tag),
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.data_out (mem_rsp_tag_b)
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);
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end
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if (PASSTHRU != 0) begin
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`UNUSED_VAR (core_req_valid_b)
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`UNUSED_VAR (core_req_rw_b)
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`UNUSED_VAR (core_req_addr_b)
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`UNUSED_VAR (core_req_byteen_b)
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`UNUSED_VAR (core_req_data_b)
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`UNUSED_VAR (core_req_tag_b)
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assign core_req_ready_b = '0;
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assign core_rsp_valid_b = '0;
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assign core_rsp_data_b = '0;
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assign core_rsp_tag_b = '0;
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`UNUSED_VAR (core_rsp_ready_b)
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assign mem_req_valid_b = 0;
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assign mem_req_addr_b = '0;
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assign mem_req_rw_b = '0;
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assign mem_req_byteen_b = '0;
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assign mem_req_data_b = '0;
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assign mem_req_tag_b = '0;
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`UNUSED_VAR (mem_req_ready_b)
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`UNUSED_VAR (mem_rsp_valid_b)
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`UNUSED_VAR (mem_rsp_data_b)
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`UNUSED_VAR (mem_rsp_tag_b)
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assign mem_rsp_ready_b = 0;
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`ifdef PERF_ENABLE
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assign cache_perf = '0;
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`endif
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end else begin
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VX_mem_bus_if #(
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.DATA_SIZE (WORD_SIZE),
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.TAG_WIDTH (CORE_TAG_X_WIDTH)
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) core_bus_wrap_if[NUM_REQS]();
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VX_mem_bus_if #(
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.DATA_SIZE (LINE_SIZE),
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.TAG_WIDTH (MEM_TAG_X_WIDTH)
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) mem_bus_wrap_if();
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_bus_wrap_if[i].req_valid = core_req_valid_b[i];
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assign core_bus_wrap_if[i].req_data.rw = core_req_rw_b[i];
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assign core_bus_wrap_if[i].req_data.addr = core_req_addr_b[i];
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assign core_bus_wrap_if[i].req_data.byteen = core_req_byteen_b[i];
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assign core_bus_wrap_if[i].req_data.data = core_req_data_b[i];
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assign core_bus_wrap_if[i].req_data.tag = core_req_tag_b[i];
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assign core_req_ready_b[i] = core_bus_wrap_if[i].req_ready;
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end
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_rsp_valid_b[i] = core_bus_wrap_if[i].rsp_valid;
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assign core_rsp_data_b[i] = core_bus_wrap_if[i].rsp_data.data;
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assign core_rsp_tag_b[i] = core_bus_wrap_if[i].rsp_data.tag;
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assign core_bus_wrap_if[i].rsp_ready = core_rsp_ready_b[i];
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end
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assign mem_req_valid_b = mem_bus_wrap_if.req_valid;
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assign mem_req_addr_b = mem_bus_wrap_if.req_data.addr;
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assign mem_req_rw_b = mem_bus_wrap_if.req_data.rw;
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assign mem_req_byteen_b = mem_bus_wrap_if.req_data.byteen;
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assign mem_req_data_b = mem_bus_wrap_if.req_data.data;
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assign mem_req_tag_b = mem_bus_wrap_if.req_data.tag;
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assign mem_bus_wrap_if.req_ready = mem_req_ready_b;
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assign mem_bus_wrap_if.rsp_valid = mem_rsp_valid_b;
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assign mem_bus_wrap_if.rsp_data.data = mem_rsp_data_b;
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assign mem_bus_wrap_if.rsp_data.tag = mem_rsp_tag_b;
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assign mem_rsp_ready_b = mem_bus_wrap_if.rsp_ready;
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`RESET_RELAY (cache_reset, reset);
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VX_cache #(
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.INSTANCE_ID (INSTANCE_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.LINE_SIZE (LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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|
.NUM_WAYS (NUM_WAYS),
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|
.WORD_SIZE (WORD_SIZE),
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|
.NUM_REQS (NUM_REQS),
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|
.CRSQ_SIZE (CRSQ_SIZE),
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|
.MSHR_SIZE (MSHR_SIZE),
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|
.MRSQ_SIZE (MRSQ_SIZE),
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|
.MREQ_SIZE (MREQ_SIZE),
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|
.WRITE_ENABLE (WRITE_ENABLE),
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|
.UUID_WIDTH (UUID_WIDTH),
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.TAG_WIDTH (CORE_TAG_X_WIDTH),
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.CORE_OUT_REG (NC_BYPASS ? 1 : CORE_OUT_REG),
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.MEM_OUT_REG (NC_BYPASS ? 1 : MEM_OUT_REG)
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) cache (
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.clk (clk),
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|
.reset (cache_reset),
|
|
|
|
`ifdef PERF_ENABLE
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.cache_perf (cache_perf),
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`endif
|
|
|
|
.core_bus_if (core_bus_wrap_if),
|
|
.mem_bus_if (mem_bus_wrap_if)
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|
);
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|
|
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end
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|
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|
`ifdef DBG_TRACE_CACHE_BANK
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|
|
|
for (genvar i = 0; i < NUM_REQS; ++i) begin
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|
wire [`UP(UUID_WIDTH)-1:0] core_req_uuid;
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|
wire [`UP(UUID_WIDTH)-1:0] core_rsp_uuid;
|
|
|
|
if (UUID_WIDTH != 0) begin
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|
assign core_req_uuid = core_bus_if[i].req_data.tag[TAG_WIDTH-1 -: UUID_WIDTH];
|
|
assign core_rsp_uuid = core_bus_if[i].rsp_data.tag[TAG_WIDTH-1 -: UUID_WIDTH];
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|
end else begin
|
|
assign core_req_uuid = 0;
|
|
assign core_rsp_uuid = 0;
|
|
end
|
|
|
|
wire core_req_fire = core_bus_if[i].req_valid && core_bus_if[i].req_ready;
|
|
wire core_rsp_fire = core_bus_if[i].rsp_valid && core_bus_if[i].rsp_ready;
|
|
|
|
always @(posedge clk) begin
|
|
if (core_req_fire) begin
|
|
if (core_bus_if[i].req_data.rw)
|
|
`TRACE(1, ("%d: %s core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(core_bus_if[i].req_data.addr), core_bus_if[i].req_data.tag, i, core_bus_if[i].req_data.byteen, core_bus_if[i].req_data.data, core_req_uuid));
|
|
else
|
|
`TRACE(1, ("%d: %s core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(core_bus_if[i].req_data.addr), core_bus_if[i].req_data.tag, i, core_req_uuid));
|
|
end
|
|
if (core_rsp_fire) begin
|
|
`TRACE(1, ("%d: %s core-rd-rsp: tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, core_bus_if[i].rsp_data.tag, i, core_bus_if[i].rsp_data.data, core_rsp_uuid));
|
|
end
|
|
end
|
|
end
|
|
|
|
wire [`UP(UUID_WIDTH)-1:0] mem_req_uuid;
|
|
wire [`UP(UUID_WIDTH)-1:0] mem_rsp_uuid;
|
|
|
|
if ((UUID_WIDTH != 0) && (NC_BYPASS != 0)) begin
|
|
assign mem_req_uuid = mem_bus_if.req_data.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
|
|
assign mem_rsp_uuid = mem_bus_if.rsp_data.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
|
|
end else begin
|
|
assign mem_req_uuid = 0;
|
|
assign mem_rsp_uuid = 0;
|
|
end
|
|
|
|
wire mem_req_fire = mem_bus_if.req_valid && mem_bus_if.req_ready;
|
|
wire mem_rsp_fire = mem_bus_if.rsp_valid && mem_bus_if.rsp_ready;
|
|
|
|
always @(posedge clk) begin
|
|
if (mem_req_fire) begin
|
|
if (mem_bus_if.req_data.rw)
|
|
`TRACE(1, ("%d: %s mem-wr-req: addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n",
|
|
$time, INSTANCE_ID, `TO_FULL_ADDR(mem_bus_if.req_data.addr), mem_bus_if.req_data.tag, mem_bus_if.req_data.byteen, mem_bus_if.req_data.data, mem_req_uuid));
|
|
else
|
|
`TRACE(1, ("%d: %s mem-rd-req: addr=0x%0h, tag=0x%0h (#%0d)\n",
|
|
$time, INSTANCE_ID, `TO_FULL_ADDR(mem_bus_if.req_data.addr), mem_bus_if.req_data.tag, mem_req_uuid));
|
|
end
|
|
if (mem_rsp_fire) begin
|
|
`TRACE(1, ("%d: %s mem-rd-rsp: tag=0x%0h, data=0x%0h (#%0d)\n",
|
|
$time, INSTANCE_ID, mem_bus_if.rsp_data.tag, mem_bus_if.rsp_data.data, mem_rsp_uuid));
|
|
end
|
|
end
|
|
`endif
|
|
|
|
endmodule
|