vortex_afu.json

+define+GLOBAL_BLOCK_SIZE_BYTES=64

+incdir+.
+incdir+../rtl
+incdir+../rtl/shared_memory
+incdir+../rtl/cache
+incdir+../rtl/generic_cache
+incdir+../rtl/interfaces
+incdir+../rtl/pipe_regs
+incdir+../rtl/compat

../rtl/VX_user_config.vh
../rtl/VX_config.vh
../rtl/VX_define.vh
../rtl/generic_cache/VX_cache_config.vh
../rtl/Vortex_Socket.v
../rtl/Vortex_Cluster.v
../rtl/Vortex.v
../rtl/VX_front_end.v
../rtl/VX_back_end.v
../rtl/VX_fetch.v
../rtl/VX_scheduler.v
../rtl/VX_execute_unit.v
../rtl/VX_warp.v
../rtl/VX_icache_stage.v
../rtl/VX_gpr_wrapper.v
../rtl/byte_enabled_simple_dual_port_ram.v
../rtl/VX_gpgpu_inst.v
../rtl/VX_writeback.v
../rtl/VX_countones.v
../rtl/VX_csr_handler.v
../rtl/VX_csr_pipe.v
../rtl/VX_generic_queue_ll.v
../rtl/VX_warp_scheduler.v
../rtl/VX_priority_encoder.v
../rtl/VX_generic_queue.v
../rtl/pipe_regs/VX_f_d_reg.v
../rtl/pipe_regs/VX_i_d_reg.v
../rtl/pipe_regs/VX_d_e_reg.v
../rtl/VX_gpr.v
../rtl/VX_gpr_stage.v
../rtl/VX_dmem_controller.v
../rtl/VX_alu.v
../rtl/VX_generic_stack.v
../rtl/VX_generic_priority_encoder.v
../rtl/VX_csr_data.v
../rtl/VX_lsu.v
../rtl/VX_decode.v
../rtl/VX_inst_multiplex.v
../rtl/VX_csr_wrapper.v
../rtl/VX_priority_encoder_w_mask.v
../rtl/VX_generic_register.v
../rtl/VX_lsu_addr_gen.v
../rtl/compat/VX_mult.v
../rtl/compat/VX_divide.v
../rtl/generic_cache/VX_snp_fwd_arb.v
../rtl/generic_cache/VX_cache_dram_req_arb.v
../rtl/generic_cache/VX_cache_dfq_queue.v
../rtl/generic_cache/VX_cache_wb_sel_merge.v
../rtl/generic_cache/VX_mrv_queue.v
../rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v
../rtl/generic_cache/VX_tag_data_access.v
../rtl/generic_cache/generic_cache.v
../rtl/generic_cache/VX_cache_core_req_bank_sel.v
../rtl/generic_cache/VX_cache_req_queue.v
../rtl/generic_cache/VX_bank.v
../rtl/generic_cache/VX_cache_miss_resrv.v
../rtl/generic_cache/VX_fill_invalidator.v
../rtl/generic_cache/VX_tag_data_structure.v
../rtl/generic_cache/VX_prefetcher.v
../rtl/cache/VX_generic_pe.v
../rtl/cache/cache_set.v
../rtl/cache/VX_d_cache.v
../rtl/cache/VX_Cache_Bank.v
../rtl/cache/VX_cache_data_per_index.v
../rtl/cache/VX_d_cache_encapsulate.v
../rtl/cache/VX_cache_bank_valid.v
../rtl/cache/VX_cache_data.v
../rtl/shared_memory/VX_shared_memory_block.v
../rtl/shared_memory/VX_priority_encoder_sm.v
../rtl/shared_memory/VX_shared_memory.v
../rtl/shared_memory/VX_bank_valids.v
../rtl/interfaces/VX_exec_unit_req_inter.v
../rtl/interfaces/VX_branch_response_inter.v
../rtl/interfaces/VX_inst_meta_inter.v
../rtl/interfaces/VX_join_inter.v
../rtl/interfaces/VX_icache_response_inter.v
../rtl/interfaces/VX_inst_exec_wb_inter.v
../rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
../rtl/interfaces/VX_csr_req_inter.v
../rtl/interfaces/VX_icache_request_inter.v
../rtl/interfaces/VX_gpu_dcache_rsp_inter.v
../rtl/interfaces/VX_frE_to_bckE_req_inter.v
../rtl/interfaces/VX_dram_req_rsp_inter.v
../rtl/interfaces/VX_dcache_request_inter.v
../rtl/interfaces/VX_gpr_data_inter.v
../rtl/interfaces/VX_dcache_response_inter.v
../rtl/interfaces/VX_csr_wb_inter.v
../rtl/interfaces/VX_gpu_dcache_req_inter.v
../rtl/interfaces/VX_lsu_req_inter.v
../rtl/interfaces/VX_gpu_snp_req_rsp.v
../rtl/interfaces/VX_mw_wb_inter.v
../rtl/interfaces/VX_gpr_jal_inter.v
../rtl/interfaces/VX_gpu_inst_req_inter.v
../rtl/interfaces/VX_wstall_inter.v
../rtl/interfaces/VX_wb_inter.v
../rtl/interfaces/VX_gpr_read_inter.v
../rtl/interfaces/VX_mem_req_inter.v
../rtl/interfaces/VX_jal_response_inter.v
../rtl/interfaces/VX_warp_ctl_inter.v
../rtl/interfaces/VX_gpu_dcache_snp_req_inter.v
../rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v
../rtl/interfaces/VX_inst_mem_wb_inter.v

ccip_interface_reg.sv
ccip_std_afu.sv
vortex_afu.sv