// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header

#include "Vcache_simX.h"
#include "Vcache_simX__Syms.h"


//--------------------
// STATIC VARIABLES

CData/*1:0*/ Vcache_simX::__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[16];
CData/*0:0*/ Vcache_simX::__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[16];
IData/*31:0*/ Vcache_simX::__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[16];
CData/*1:0*/ Vcache_simX::__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[16];
CData/*0:0*/ Vcache_simX::__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[16];
IData/*31:0*/ Vcache_simX::__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[16];
CData/*1:0*/ Vcache_simX::__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[16];
CData/*0:0*/ Vcache_simX::__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[16];
IData/*31:0*/ Vcache_simX::__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[16];
CData/*1:0*/ Vcache_simX::__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[16];
CData/*0:0*/ Vcache_simX::__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[16];
IData/*31:0*/ Vcache_simX::__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[16];
CData/*1:0*/ Vcache_simX::__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[16];
CData/*0:0*/ Vcache_simX::__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[16];
IData/*31:0*/ Vcache_simX::__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[16];
CData/*1:0*/ Vcache_simX::__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[16];
CData/*0:0*/ Vcache_simX::__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[16];
IData/*31:0*/ Vcache_simX::__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[16];
CData/*1:0*/ Vcache_simX::__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[16];
CData/*0:0*/ Vcache_simX::__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[16];
IData/*31:0*/ Vcache_simX::__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i[16];
CData/*1:0*/ Vcache_simX::__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index[16];
CData/*0:0*/ Vcache_simX::__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found[16];
IData/*31:0*/ Vcache_simX::__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[16];
CData/*1:0*/ Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[16];
CData/*0:0*/ Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[16];
IData/*31:0*/ Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16];

//--------------------

VL_CTOR_IMP(Vcache_simX) {
    Vcache_simX__Syms* __restrict vlSymsp = __VlSymsp = new Vcache_simX__Syms(this, name());
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    VL_CELL(__PVT__cache_simX__DOT__VX_dram_req_rsp_icache, Vcache_simX_VX_dram_req_rsp_inter__N1_NB4);
    VL_CELL(__PVT__cache_simX__DOT__VX_dcache_req, Vcache_simX_VX_dcache_request_inter);
    VL_CELL(__PVT__cache_simX__DOT__VX_dram_req_rsp, Vcache_simX_VX_dram_req_rsp_inter__N4_NB4);
    VL_CELL(__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi7);
    VL_CELL(__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi7);
    VL_CELL(__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi7);
    VL_CELL(__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi7);
    // Reset internal values
    
    // Reset structure values
    _ctor_var_reset();
}

void Vcache_simX::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
    if (0 && first) {}  // Prevent unused
    this->__VlSymsp = vlSymsp;
}

Vcache_simX::~Vcache_simX() {
    delete __VlSymsp; __VlSymsp=NULL;
}

//--------------------


void Vcache_simX::eval() {
    VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vcache_simX::eval\n"); );
    Vcache_simX__Syms* __restrict vlSymsp = this->__VlSymsp;  // Setup global symbol table
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
    // Debug assertions
    _eval_debug_assertions();
#endif  // VL_DEBUG
    // Initialize
    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
    // Evaluate till stable
    int __VclockLoop = 0;
    QData __Vchange = 1;
    do {
        VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
        vlSymsp->__Vm_activity = true;
        _eval(vlSymsp);
        if (VL_UNLIKELY(++__VclockLoop > 100)) {
            // About to fail, so enable debug to see what's not settling.
            // Note you must run make with OPT=-DVL_DEBUG for debug prints.
            int __Vsaved_debug = Verilated::debug();
            Verilated::debug(1);
            __Vchange = _change_request(vlSymsp);
            Verilated::debug(__Vsaved_debug);
            VL_FATAL_MT("cache_simX.v", 4, "",
                "Verilated model didn't converge\n"
                "- See DIDNOTCONVERGE in the Verilator manual");
        } else {
            __Vchange = _change_request(vlSymsp);
        }
    } while (VL_UNLIKELY(__Vchange));
}

void Vcache_simX::_eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp) {
    vlSymsp->__Vm_didInit = true;
    _eval_initial(vlSymsp);
    vlSymsp->__Vm_activity = true;
    // Evaluate till stable
    int __VclockLoop = 0;
    QData __Vchange = 1;
    do {
        _eval_settle(vlSymsp);
        _eval(vlSymsp);
        if (VL_UNLIKELY(++__VclockLoop > 100)) {
            // About to fail, so enable debug to see what's not settling.
            // Note you must run make with OPT=-DVL_DEBUG for debug prints.
            int __Vsaved_debug = Verilated::debug();
            Verilated::debug(1);
            __Vchange = _change_request(vlSymsp);
            Verilated::debug(__Vsaved_debug);
            VL_FATAL_MT("cache_simX.v", 4, "",
                "Verilated model didn't DC converge\n"
                "- See DIDNOTCONVERGE in the Verilator manual");
        } else {
            __Vchange = _change_request(vlSymsp);
        }
    } while (VL_UNLIKELY(__Vchange));
}

//--------------------
// Internal Methods

VL_INLINE_OPT void Vcache_simX::_combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_combo__TOP__1\n"); );
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read 
        = ((IData)(vlTOPp->in_icache_valid_pc_addr)
            ? ((IData)(vlTOPp->in_icache_valid_pc_addr)
                ? 2U : 7U) : 7U);
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid 
        = ((0xeU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) 
           | vlTOPp->in_dcache_in_valid[0U]);
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid 
        = ((0xdU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) 
           | (vlTOPp->in_dcache_in_valid[1U] << 1U));
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid 
        = ((0xbU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) 
           | (vlTOPp->in_dcache_in_valid[2U] << 2U));
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid 
        = ((7U & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) 
           | (vlTOPp->in_dcache_in_valid[3U] << 3U));
}

void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_settle__TOP__2\n"); );
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Variables
    WData/*31:0*/ __Vtemp19[4];
    WData/*31:0*/ __Vtemp20[4];
    WData/*31:0*/ __Vtemp21[4];
    WData/*31:0*/ __Vtemp22[4];
    // Body
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read 
        = ((IData)(vlTOPp->in_icache_valid_pc_addr)
            ? ((IData)(vlTOPp->in_icache_valid_pc_addr)
                ? 2U : 7U) : 7U);
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid 
        = ((0xeU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) 
           | vlTOPp->in_dcache_in_valid[0U]);
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid 
        = ((0xdU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) 
           | (vlTOPp->in_dcache_in_valid[1U] << 1U));
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid 
        = ((0xbU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) 
           | (vlTOPp->in_dcache_in_valid[2U] << 2U));
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid 
        = ((7U & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) 
           | (vlTOPp->in_dcache_in_valid[3U] << 3U));
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
        = vlTOPp->in_dcache_in_address[0U];
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
        = vlTOPp->in_dcache_in_address[1U];
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
        = vlTOPp->in_dcache_in_address[2U];
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
        = vlTOPp->in_dcache_in_address[3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid)
            ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid)
            : (IData)(vlTOPp->in_icache_valid_pc_addr));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid 
        = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) 
           & VL_NEGATE_I((IData)((0xffU == (0xffU & 
                                            ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                              << 8U) 
                                             | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                                >> 0x18U)))))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid 
        = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) 
           & VL_NEGATE_I((IData)((0xffU != (0xffU & 
                                            ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                              << 8U) 
                                             | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                                >> 0x18U)))))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))
            ? (IData)(vlTOPp->in_dcache_mem_read) : 7U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))
            ? (IData)(vlTOPp->in_dcache_mem_write) : 7U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid 
        = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) 
           | (1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid 
        = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) 
           | (2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid 
        = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) 
           | (4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid 
        = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) 
           | (8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write 
        = ((7U != (IData)(vlTOPp->in_dcache_mem_write)) 
           & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))
            ? (IData)(vlTOPp->in_dcache_mem_write) : 7U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))
            ? (IData)(vlTOPp->in_dcache_mem_read) : 7U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid 
        = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid))
            ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)
            : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 0U;
    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 1U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = 0U;
    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = 0U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
            ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)
            : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks 
        = (((~ ((IData)(1U) << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]))) 
            & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) 
           | ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid)) 
              << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U])));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) 
                                        + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]))))) 
            & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) 
           | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) 
                     >> 1U)) << (0xfU & ((IData)(1U) 
                                         + (0xcU & 
                                            vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U])))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) 
                                        + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U]))))) 
            & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) 
           | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) 
                     >> 2U)) << (0xfU & ((IData)(2U) 
                                         + (0xcU & 
                                            vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U])))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) 
                                        + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U]))))) 
            & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) 
           | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) 
                     >> 3U)) << (0xfU & ((IData)(3U) 
                                         + (0xcU & 
                                            vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U])))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in 
        = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
           | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
                  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
              & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
                 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
        = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
            : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
                ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
                : (vlTOPp->in_icache_pc_addr >> (0x1fU 
                                                 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) 
                                                    << 5U)))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfffeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
              & (0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                               << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                            >> 2U))))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfffdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffffffeU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                             & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                               << 0x1eU) 
                                              | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                                 >> 2U)))) 
                                << 1U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfffbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffffffcU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                             & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                               << 0x1eU) 
                                              | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                 >> 2U)))) 
                                << 2U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfff7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffffff8U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                             & ((0U == (3U & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                              >> 2U))) 
                                << 3U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xffefU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
               & (1U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                             >> 2U))))) 
              << 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xffdfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffffffe0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 4U) & ((1U == (3U 
                                                & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                    << 0x1eU) 
                                                   | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                                      >> 2U)))) 
                                        << 5U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xffbfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffffffc0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 4U) & ((1U == (3U 
                                                & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                    << 0x1eU) 
                                                   | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                      >> 2U)))) 
                                        << 6U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xff7fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffffff80U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 4U) & ((1U == (3U 
                                                & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                   >> 2U))) 
                                        << 7U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfeffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
               & (2U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                             >> 2U))))) 
              << 8U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfdffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffffe00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 8U) & ((2U == (3U 
                                                & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                    << 0x1eU) 
                                                   | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                                      >> 2U)))) 
                                        << 9U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfbffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffffc00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 8U) & ((2U == (3U 
                                                & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                    << 0x1eU) 
                                                   | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                      >> 2U)))) 
                                        << 0xaU))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xf7ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffff800U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 8U) & ((2U == (3U 
                                                & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                   >> 2U))) 
                                        << 0xbU))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xefffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
               & (3U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                             >> 2U))))) 
              << 0xcU));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xdfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffffe000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 0xcU) & ((3U == (3U 
                                                  & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                      << 0x1eU) 
                                                     | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                                        >> 2U)))) 
                                          << 0xdU))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xbfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffffc000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 0xcU) & ((3U == (3U 
                                                  & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                      << 0x1eU) 
                                                     | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                        >> 2U)))) 
                                          << 0xeU))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0x7fffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffff8000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 0xcU) & ((3U == (3U 
                                                  & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                     >> 2U))) 
                                          << 0xfU))));
    vlTOPp->__Vtableidx6 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index 
        = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index
        [vlTOPp->__Vtableidx6];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found 
        = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found
        [vlTOPp->__Vtableidx6];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i 
        = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i
        [vlTOPp->__Vtableidx6];
    vlTOPp->__Vtableidx7 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) 
                                    >> 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index 
        = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index
        [vlTOPp->__Vtableidx7];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found 
        = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found
        [vlTOPp->__Vtableidx7];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i 
        = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i
        [vlTOPp->__Vtableidx7];
    vlTOPp->__Vtableidx8 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) 
                                    >> 8U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index 
        = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index
        [vlTOPp->__Vtableidx8];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found 
        = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found
        [vlTOPp->__Vtableidx8];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i 
        = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i
        [vlTOPp->__Vtableidx8];
    vlTOPp->__Vtableidx9 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) 
                                    >> 0xcU));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index 
        = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index
        [vlTOPp->__Vtableidx9];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found 
        = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found
        [vlTOPp->__Vtableidx9];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i 
        = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i
        [vlTOPp->__Vtableidx9];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem 
        = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
           & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access 
        = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
           & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__sb_mask 
        = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
            ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
                     ? 2U : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
                              ? 4U : 8U)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[0U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[1U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[2U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[3U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[4U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[5U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[6U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[7U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
        = ((VL_ULL(0x3fffff800000) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) 
           | (IData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
                             [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                        >> 4U))])));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
        = ((VL_ULL(0x7fffff) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) 
           | ((QData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
                              [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                         >> 4U))])) 
              << 0x17U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) 
           | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
           [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                      >> 4U))]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) 
           | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
              [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                         >> 4U))] << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = 0U;
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
    }
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
    }
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids = 0U;
    if ((0x80U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)));
    }
    if ((0x40U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)));
    }
    if ((0x20U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)));
    }
    if ((0x10U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)));
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids = 0U;
    if ((0x800U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)));
    }
    if ((0x400U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)));
    }
    if ((0x200U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)));
    }
    if ((0x100U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)));
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids = 0U;
    if ((0x8000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)));
    }
    if ((0x4000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)));
    }
    if ((0x2000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)));
    }
    if ((0x1000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)));
    }
    vlTOPp->__Vtableidx1 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index 
        = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index
        [vlTOPp->__Vtableidx1];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found 
        = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found
        [vlTOPp->__Vtableidx1];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i 
        = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i
        [vlTOPp->__Vtableidx1];
    vlTOPp->__Vtableidx2 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) 
                                    >> 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index 
        = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index
        [vlTOPp->__Vtableidx2];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found 
        = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found
        [vlTOPp->__Vtableidx2];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i 
        = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i
        [vlTOPp->__Vtableidx2];
    vlTOPp->__Vtableidx3 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) 
                                    >> 8U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index 
        = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index
        [vlTOPp->__Vtableidx3];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found 
        = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found
        [vlTOPp->__Vtableidx3];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i 
        = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i
        [vlTOPp->__Vtableidx3];
    vlTOPp->__Vtableidx4 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) 
                                    >> 0xcU));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index 
        = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index
        [vlTOPp->__Vtableidx4];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found 
        = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found
        [vlTOPp->__Vtableidx4];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i 
        = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i
        [vlTOPp->__Vtableidx4];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank 
        = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) 
           | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank 
        = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found)
               ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index)))
               : 0U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank 
        = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) 
           | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank 
        = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank 
        = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found)
                ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index)))
                : 0U) << 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank 
        = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank 
        = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank 
        = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found)
                ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index)))
                : 0U) << 8U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank 
        = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index) 
              << 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank 
        = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found) 
              << 3U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank 
        = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found)
                ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index)))
                : 0U) << 0xcU));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank 
        = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index) 
              << 6U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
            ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0U]
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
            ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[1U]
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
            ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[2U]
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
            ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[3U]
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
        = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
               ? 0xfU : 0U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
        = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
                ? 0xfU : 0U) << 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
        = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
                ? 0xfU : 0U) << 8U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
        = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
                ? 0xfU : 0U) << 0xcU));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) 
           | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 0U;
    if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
                  >> 1U)))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U;
    }
    if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U;
    if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
                  >> 1U)))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 1U;
    }
    if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
               & ((0x7fffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way)) 
                  == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                   >> 9U)))) ? 1U : 0U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) 
           | (((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
                 >> 1U) & ((0x7fffffU & (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
                                                 >> 0x17U))) 
                           == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                            >> 9U))))
                ? 1U : 0U) << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid 
        = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
           | (1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid 
        = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
           | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid 
        = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
           | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid 
        = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
           | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)) 
              << 3U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num 
        = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) 
           | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid 
        = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) 
           | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num 
        = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid 
        = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num 
        = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index) 
              << 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid 
        = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num 
        = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index) 
              << 6U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid 
        = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found) 
              << 3U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in 
        = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) 
           | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                  & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) 
              & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in 
        = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) 
           | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                  & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) 
              & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
                    >> 1U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in 
        = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) 
           | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                  & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) 
              & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
                    >> 2U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in 
        = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) 
           | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                  & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) 
              & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
                    >> 3U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
        = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
            : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
                ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
                : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
               (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
        = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
            : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
                ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
                : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
               (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
                      >> 2U))]));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
        = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
            : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
                ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
                : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
               (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
                      >> 4U))]));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
        = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
            : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
                ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
                : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
               (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
                      >> 6U))]));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
    }
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U;
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 1U;
    }
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) 
           | ((IData)(1U) << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) 
           | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                    >> 2U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) 
           | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                    >> 4U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) 
           | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                    >> 6U))));
    __Vtemp19[0U] = 0U;
    __Vtemp19[1U] = 0U;
    __Vtemp19[2U] = 0U;
    __Vtemp19[3U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U] 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
            ? __Vtemp19[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))]
            : 0U);
    __Vtemp20[0U] = 0U;
    __Vtemp20[1U] = 0U;
    __Vtemp20[2U] = 0U;
    __Vtemp20[3U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U] 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
            ? __Vtemp20[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                               >> 2U))] : 0U);
    __Vtemp21[0U] = 0U;
    __Vtemp21[1U] = 0U;
    __Vtemp21[2U] = 0U;
    __Vtemp21[3U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U] 
        = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
            ? __Vtemp21[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                               >> 4U))] : 0U);
    __Vtemp22[0U] = 0U;
    __Vtemp22[1U] = 0U;
    __Vtemp22[2U] = 0U;
    __Vtemp22[3U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U] 
        = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
            ? __Vtemp22[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                               >> 6U))] : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write 
        = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) 
           & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write 
        = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) 
           & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) 
              >> 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write 
        = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) 
           & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) 
              >> 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write 
        = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) 
           & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) 
              >> 3U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
            ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
           (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))]
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
            ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
           (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                  >> 2U))] : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
        = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
            ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
           (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                  >> 4U))] : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
        = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
            ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
           (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                  >> 6U))] : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
            ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update)
            : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
           & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we = 0U;
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we 
                                = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) 
                                   | (3U & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                             << 0x1cU) 
                                            | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                               >> 4U))));
                        }
                    }
                }
            }
        }
    }
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we 
                                = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) 
                                   | (0xcU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                               << 0x1eU) 
                                              | (0x3ffffffcU 
                                                 & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                    >> 2U)))));
                        }
                    }
                }
            }
        }
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we 
                                = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) 
                                   | (0x30U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U]));
                        }
                    }
                }
            }
        }
    }
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                >> 0x18U)))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we 
                                = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) 
                                   | (0xc0U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                               << 2U)));
                        }
                    }
                }
            }
        }
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU] = 0U;
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            VL_ASSIGNSEL_WIII(32,(0x60U 
                                                  & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                                     << 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, 
                                              vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U]);
                        }
                    }
                }
            }
        }
    }
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            VL_ASSIGNSEL_WIII(32,(0x1ffU 
                                                  & ((IData)(0x80U) 
                                                     + 
                                                     (0x60U 
                                                      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                         << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, 
                                              vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U]);
                        }
                    }
                }
            }
        }
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            VL_ASSIGNSEL_WIII(32,(0x1ffU 
                                                  & ((IData)(0x100U) 
                                                     + 
                                                     (0x60U 
                                                      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                         << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, 
                                              vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U]);
                        }
                    }
                }
            }
        }
    }
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                >> 0x18U)))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            VL_ASSIGNSEL_WIII(32,(0x1ffU 
                                                  & ((IData)(0x180U) 
                                                     + 
                                                     (0x60U 
                                                      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                         << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, 
                                              vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U]);
                        }
                    }
                }
            }
        }
    }
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid 
                                    = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) 
                                       | ((IData)(1U) 
                                          << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid 
                                    = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) 
                                       | ((IData)(1U) 
                                          << (3U & 
                                              ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                               >> 3U))));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid 
                                    = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) 
                                       | ((IData)(1U) 
                                          << (3U & 
                                              ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                               >> 6U))));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                >> 0x18U)))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid 
                                    = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) 
                                       | ((IData)(1U) 
                                          << (3U & 
                                              ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                               >> 9U))));
                            }
                        }
                    }
                }
            }
        }
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = 0U;
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 
                                = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                             << 0x1aU) 
                                            | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                               >> 6U)));
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                = ((0xfffff80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                   | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1));
                        }
                    }
                }
            } else {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 
                                    = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                 << 0x1aU) 
                                                | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                                   >> 6U)));
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                    = ((0xfffff80U 
                                        & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                       | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2));
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    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 
                                = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                             << 0x1aU) 
                                            | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                               >> 6U)));
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                = ((0xfffc07fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) 
                                      << 7U));
                        }
                    }
                }
            } else {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 
                                    = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                 << 0x1aU) 
                                                | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                   >> 6U)));
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                    = ((0xfffc07fU 
                                        & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                       | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) 
                                          << 7U));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 
                                = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                             << 0x1aU) 
                                            | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                               >> 6U)));
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                = ((0xfe03fffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) 
                                      << 0xeU));
                        }
                    }
                }
            } else {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 
                                    = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                 << 0x1aU) 
                                                | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                   >> 6U)));
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                    = ((0xfe03fffU 
                                        & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                       | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) 
                                          << 0xeU));
                            }
                        }
                    }
                }
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        }
    }
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                >> 0x18U)))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 
                                = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                            >> 6U));
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) 
                                      << 0x15U));
                        }
                    }
                }
            } else {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 
                                    = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                >> 6U));
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                    = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                       | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) 
                                          << 0x15U));
                            }
                        }
                    }
                }
            }
        }
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) 
              & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
        = ((0xffff0000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)
               ? 0U : (0xffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) 
               & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
        = ((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)
                ? (0xffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we))
                : 0U) << 0x10U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual 
        = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) 
            | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))
            ? (((0U == (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                  << 7U) + (0x60U & 
                                            (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                             << 3U)))))
                 ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                         ((IData)(1U) + (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                 << 7U) 
                                                + (0x60U 
                                                   & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                      << 3U))) 
                                               >> 5U)))] 
                         << ((IData)(0x20U) - (0x1fU 
                                               & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                   << 7U) 
                                                  + 
                                                  (0x60U 
                                                   & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                      << 3U))))))) 
               | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                  (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                           << 7U) + (0x60U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                              << 3U))) 
                         >> 5U))] >> (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                << 7U) 
                                               + (0x60U 
                                                  & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                     << 3U))))))
            : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
                ? ((((0U == (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                       << 7U) + (0x60U 
                                                 & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                    << 3U)))))
                      ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                              ((IData)(1U) + (7U & 
                                              ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                 << 7U) 
                                                + (0x60U 
                                                   & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                      << 3U))) 
                                               >> 5U)))] 
                              << ((IData)(0x20U) - 
                                  (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                             << 7U) 
                                            + (0x60U 
                                               & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                  << 3U))))))) 
                    | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                       (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                << 7U) + (0x60U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                   << 3U))) 
                              >> 5U))] >> (0x1fU & 
                                           (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                             << 7U) 
                                            + (0x60U 
                                               & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                  << 3U)))))) 
                   >> 8U) : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
                              ? ((((0U == (0x1fU & 
                                           (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                             << 7U) 
                                            + (0x60U 
                                               & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                  << 3U)))))
                                    ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                                            ((IData)(1U) 
                                             + (7U 
                                                & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                     << 7U) 
                                                    + 
                                                    (0x60U 
                                                     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                        << 3U))) 
                                                   >> 5U)))] 
                                            << ((IData)(0x20U) 
                                                - (0x1fU 
                                                   & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                       << 7U) 
                                                      + 
                                                      (0x60U 
                                                       & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                          << 3U))))))) 
                                  | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                                     (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                              << 7U) 
                                             + (0x60U 
                                                & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                   << 3U))) 
                                            >> 5U))] 
                                     >> (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                   << 7U) 
                                                  + 
                                                  (0x60U 
                                                   & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                      << 3U)))))) 
                                 >> 0x10U) : ((((0U 
                                                 == 
                                                 (0x1fU 
                                                  & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                      << 7U) 
                                                     + 
                                                     (0x60U 
                                                      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                         << 3U)))))
                                                 ? 0U
                                                 : 
                                                (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                                                 ((IData)(1U) 
                                                  + 
                                                  (7U 
                                                   & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                        << 7U) 
                                                       + 
                                                       (0x60U 
                                                        & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                           << 3U))) 
                                                      >> 5U)))] 
                                                 << 
                                                 ((IData)(0x20U) 
                                                  - 
                                                  (0x1fU 
                                                   & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                       << 7U) 
                                                      + 
                                                      (0x60U 
                                                       & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                          << 3U))))))) 
                                               | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                                                  (7U 
                                                   & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                        << 7U) 
                                                       + 
                                                       (0x60U 
                                                        & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                           << 3U))) 
                                                      >> 5U))] 
                                                  >> 
                                                  (0x1fU 
                                                   & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                       << 7U) 
                                                      + 
                                                      (0x60U 
                                                       & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                          << 3U)))))) 
                                              >> 0x18U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
        = ((0x2dU >= (0x3fU & ((IData)(0x17U) * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))
            ? (0x7fffffU & (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
                                    >> (0x3fU & ((IData)(0x17U) 
                                                 * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))))
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use 
        = (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
                 >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests 
        = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
            ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
               & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))
            : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) 
               & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[1U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[2U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[3U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[4U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 7U))][0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[5U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 7U))][1U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[6U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 7U))][2U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[7U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 7U))][3U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[8U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0xeU))][0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[9U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0xeU))][1U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xaU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0xeU))][2U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xbU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0xeU))][3U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xcU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0x15U))][0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xdU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0x15U))][1U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xeU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0x15U))][2U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xfU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0x15U))][3U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank 
        = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) 
            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
               == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                >> 9U)))) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use));
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                VL_ASSIGNSEL_WIII(32,
                                                  (0x60U 
                                                   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                                      << 5U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, 
                                                  vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                  (3U 
                                                   & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                                      >> 4U))]);
                            }
                        }
                    }
                }
            }
        }
    }
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                VL_ASSIGNSEL_WIII(32,
                                                  (0x60U 
                                                   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                                      << 2U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, 
                                                  (((0U 
                                                     == 
                                                     (0x1fU 
                                                      & ((IData)(0x80U) 
                                                         + 
                                                         (0x60U 
                                                          & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                             << 1U)))))
                                                     ? 0U
                                                     : 
                                                    (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                     ((IData)(1U) 
                                                      + 
                                                      (0xfU 
                                                       & (((IData)(0x80U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                               << 1U))) 
                                                          >> 5U)))] 
                                                     << 
                                                     ((IData)(0x20U) 
                                                      - 
                                                      (0x1fU 
                                                       & ((IData)(0x80U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                              << 1U))))))) 
                                                   | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                      (0xfU 
                                                       & (((IData)(0x80U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                               << 1U))) 
                                                          >> 5U))] 
                                                      >> 
                                                      (0x1fU 
                                                       & ((IData)(0x80U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                              << 1U)))))));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                VL_ASSIGNSEL_WIII(32,
                                                  (0x60U 
                                                   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                                      >> 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, 
                                                  (((0U 
                                                     == 
                                                     (0x1fU 
                                                      & ((IData)(0x100U) 
                                                         + 
                                                         (0x60U 
                                                          & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                             << 1U)))))
                                                     ? 0U
                                                     : 
                                                    (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                     ((IData)(1U) 
                                                      + 
                                                      (0xfU 
                                                       & (((IData)(0x100U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                               << 1U))) 
                                                          >> 5U)))] 
                                                     << 
                                                     ((IData)(0x20U) 
                                                      - 
                                                      (0x1fU 
                                                       & ((IData)(0x100U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                              << 1U))))))) 
                                                   | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                      (0xfU 
                                                       & (((IData)(0x100U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                               << 1U))) 
                                                          >> 5U))] 
                                                      >> 
                                                      (0x1fU 
                                                       & ((IData)(0x100U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                              << 1U)))))));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                >> 0x18U)))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                VL_ASSIGNSEL_WIII(32,
                                                  (0x60U 
                                                   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                                      >> 4U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, 
                                                  (((0U 
                                                     == 
                                                     (0x1fU 
                                                      & ((IData)(0x180U) 
                                                         + 
                                                         (0x60U 
                                                          & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                             << 1U)))))
                                                     ? 0U
                                                     : 
                                                    (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                     ((IData)(1U) 
                                                      + 
                                                      (0xfU 
                                                       & (((IData)(0x180U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                               << 1U))) 
                                                          >> 5U)))] 
                                                     << 
                                                     ((IData)(0x20U) 
                                                      - 
                                                      (0x1fU 
                                                       & ((IData)(0x180U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                              << 1U))))))) 
                                                   | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                      (0xfU 
                                                       & (((IData)(0x180U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                               << 1U))) 
                                                          >> 5U))] 
                                                      >> 
                                                      (0x1fU 
                                                       & ((IData)(0x180U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                              << 1U)))))));
                            }
                        }
                    }
                }
            }
        }
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = 0U;
    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read 
            = (((~ ((IData)(0xffffffffU) << (0x1fU 
                                             & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) 
                                                << 5U)))) 
                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read) 
               | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)
                    ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
                        ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                            ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                            : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
                        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
                            ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                                ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                                : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
                            : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
                                ? (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                                : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
                                    ? (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                                    : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))
                    : 0U) << (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) 
                                       << 5U))));
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
           & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 0U;
    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 1U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U;
    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state 
        = (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss))
            ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
                     ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
                              & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))
                              ? 2U : 0U)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank 
        = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)
             ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index))
             : 0U) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask
           [0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read
            : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) 
           & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)));
    vlTOPp->out_icache_stall = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) 
                                | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)));
}

VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_settle__TOP__3\n"); );
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb 
        = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) 
           | (1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
                    >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0U] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[1U] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[2U] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[3U] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U] 
        = ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
            << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank 
        = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) 
           | (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) 
               & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
                  == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                   >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U] 
        = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
            ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
                    ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
                    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
                : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
                        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
                        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
                    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                        ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
                        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                            ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
                            : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb 
        = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) 
           | (2U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
                     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) 
                    << 1U)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[4U] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[5U] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[6U] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[7U] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[1U] 
        = ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
            << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank 
        = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) 
           | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) 
                & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
                   == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
                                    >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U] 
        = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
            ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
                    ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
                    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
                : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
                        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
                        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
                    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                        ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
                        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                            ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
                            : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb 
        = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) 
           | (4U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
                     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) 
                    << 2U)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[8U] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[9U] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xaU] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xbU] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[2U] 
        = ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
            << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank 
        = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) 
           | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) 
                & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
                   == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
                                    >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U] 
        = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
            ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
                    ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
                    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
                : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
                        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
                        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
                    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                        ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
                        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                            ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
                            : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb 
        = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) 
           | (8U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
                     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) 
                    << 3U)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xcU] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xdU] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xeU] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xfU] 
        = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[3U] 
        = ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
            << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank 
        = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) 
           | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) 
                & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
                   == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
                                    >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)) 
              << 3U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U] 
        = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
            ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
                    ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
                    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
                : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
                        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
                        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
                    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                        ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
                        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
                            ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
                            : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
           & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[0U] 
        = (0xfU & VL_NEGATE_I((IData)((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[1U] 
        = (0xfU & VL_NEGATE_I((IData)((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) 
                                             >> 1U)))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[2U] 
        = (0xfU & VL_NEGATE_I((IData)((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) 
                                             >> 2U)))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[3U] 
        = (0xfU & VL_NEGATE_I((IData)((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) 
                                             >> 3U)))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[0U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[1U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[2U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[3U] = 0U;
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
                                       << 5U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U]);
    }
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
                                       << 3U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U]);
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
                                       << 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U]);
    }
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
                                       >> 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U]);
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state 
        = (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
            & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss)))
            ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
                     ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                              & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))
                              ? 2U : 0U)));
    vlTOPp->__Vtableidx5 = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index 
        = vlTOPp->__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index
        [vlTOPp->__Vtableidx5];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found 
        = vlTOPp->__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found
        [vlTOPp->__Vtableidx5];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i 
        = vlTOPp->__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i
        [vlTOPp->__Vtableidx5];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank 
        = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) 
              & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask
              [0U]));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank 
        = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) 
           | (0xfffffff0U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) 
                             & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask
                                [1U] << 4U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank 
        = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) 
           | (0xffffff00U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) 
                             & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask
                                [2U] << 8U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank 
        = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) 
           | (0xfffff000U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) 
                             & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask
                                [3U] << 0xcU))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual 
        = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual 
        = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual) 
                   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank) 
                      >> 4U)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual 
        = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual) 
                   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank) 
                      >> 8U)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual 
        = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual) 
                   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank) 
                      >> 0xcU)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U] 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[0U]
            : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U] 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[1U]
            : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[1U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U] 
        = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[2U]
            : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[2U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U] 
        = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[3U]
            : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[3U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) 
           & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual)));
    vlTOPp->out_dcache_stall = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
                                | ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
                                   | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))));
}

VL_INLINE_OPT void Vcache_simX::_sequent__TOP__4(Vcache_simX__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_sequent__TOP__4\n"); );
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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    CData/*6:0*/ __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32;
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    CData/*7:0*/ __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35;
    CData/*0:0*/ __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35;
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    CData/*7:0*/ __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36;
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        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U;
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    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U;
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    if (vlTOPp->reset) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U;
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    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U;
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    if (vlTOPp->reset) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U;
        while (VL_GTS_III(1,32,32, 0x80U, vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind)) {
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][0U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][1U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][2U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][3U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind 
                = ((IData)(1U) + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind);
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    } else {
        if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) {
            VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                           << 5U)), 
                              vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
                              [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)], 
                              vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[
                              (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we))]);
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    if (vlTOPp->reset) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U;
        while (VL_GTS_III(1,32,32, 0x80U, vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind)) {
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][0U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][1U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][2U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][3U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind 
                = ((IData)(1U) + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind);
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    } else {
        if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) {
            VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                           << 3U)), 
                              vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
                              [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                         >> 7U))], 
                              (((0U == (0x1fU & ((IData)(0x80U) 
                                                 + 
                                                 (0x60U 
                                                  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                     << 3U)))))
                                 ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[
                                         ((IData)(1U) 
                                          + (0xfU & 
                                             (((IData)(0x80U) 
                                               + (0x60U 
                                                  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                     << 3U))) 
                                              >> 5U)))] 
                                         << ((IData)(0x20U) 
                                             - (0x1fU 
                                                & ((IData)(0x80U) 
                                                   + 
                                                   (0x60U 
                                                    & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                       << 3U))))))) 
                               | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[
                                  (0xfU & (((IData)(0x80U) 
                                            + (0x60U 
                                               & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                  << 3U))) 
                                           >> 5U))] 
                                  >> (0x1fU & ((IData)(0x80U) 
                                               + (0x60U 
                                                  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                     << 3U)))))));
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U;
        while (VL_GTS_III(1,32,32, 0x80U, vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)) {
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][0U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][1U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][2U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][3U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind 
                = ((IData)(1U) + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind);
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    } else {
        if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) {
            VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                           << 1U)), 
                              vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
                              [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                         >> 0xeU))], 
                              (((0U == (0x1fU & ((IData)(0x100U) 
                                                 + 
                                                 (0x60U 
                                                  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                     << 1U)))))
                                 ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[
                                         ((IData)(1U) 
                                          + (0xfU & 
                                             (((IData)(0x100U) 
                                               + (0x60U 
                                                  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                     << 1U))) 
                                              >> 5U)))] 
                                         << ((IData)(0x20U) 
                                             - (0x1fU 
                                                & ((IData)(0x100U) 
                                                   + 
                                                   (0x60U 
                                                    & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                       << 1U))))))) 
                               | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[
                                  (0xfU & (((IData)(0x100U) 
                                            + (0x60U 
                                               & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                  << 1U))) 
                                           >> 5U))] 
                                  >> (0x1fU & ((IData)(0x100U) 
                                               + (0x60U 
                                                  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                     << 1U)))))));
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U;
        while (VL_GTS_III(1,32,32, 0x80U, vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)) {
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][0U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][1U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][2U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU 
                                                                                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][3U] = 0U;
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind 
                = ((IData)(1U) + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind);
        }
    } else {
        if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) {
            VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                           >> 1U)), 
                              vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
                              [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                         >> 0x15U))], 
                              (((0U == (0x1fU & ((IData)(0x180U) 
                                                 + 
                                                 (0x60U 
                                                  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                     >> 1U)))))
                                 ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[
                                         ((IData)(1U) 
                                          + (0xfU & 
                                             (((IData)(0x180U) 
                                               + (0x60U 
                                                  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                     >> 1U))) 
                                              >> 5U)))] 
                                         << ((IData)(0x20U) 
                                             - (0x1fU 
                                                & ((IData)(0x180U) 
                                                   + 
                                                   (0x60U 
                                                    & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                       >> 1U))))))) 
                               | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[
                                  (0xfU & (((IData)(0x180U) 
                                            + (0x60U 
                                               & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                  >> 1U))) 
                                           >> 5U))] 
                                  >> (0x1fU & ((IData)(0x180U) 
                                               + (0x60U 
                                                  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
                                                     >> 1U)))))));
        }
    }
    vlTOPp->cache_simX__DOT__icache_i_m_ready = ((~ (IData)(vlTOPp->reset)) 
                                                 & (1U 
                                                    == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)));
    vlTOPp->cache_simX__DOT__dcache_i_m_ready = ((~ (IData)(vlTOPp->reset)) 
                                                 & (1U 
                                                    == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read 
        = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[0U] 
        = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[1U] 
        = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[2U] 
        = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[3U] 
        = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]);
    if (vlTOPp->reset) {
        __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v0 = 1U;
    } else {
        if ((1U & (((~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) 
                    & (0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
                                         >> 0x10U)))) 
                   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
                      >> 1U)))) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
                = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
                    ? 0U : (1U & (0U != (0xffffU & 
                                         (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
                                          >> 0x10U)))));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
    }
    if (vlTOPp->reset) {
        __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v0 = 1U;
    } else {
        if ((1U & (((~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) 
                    & (0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) 
                   | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
                = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
                    ? 0U : (1U & (0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests 
        = ((IData)(vlTOPp->reset) ? 0U : ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))
                                           ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests)
                                           : 0U));
    if (vlTOPp->reset) {
        __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v0 = 1U;
    } else {
        if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) {
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
    }
    if (vlTOPp->reset) {
        __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0 = 1U;
    } else {
        if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) {
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
    }
    if (vlTOPp->reset) {
        __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v0 = 1U;
    } else {
        if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
                = (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                >> 9U));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
    }
    if (vlTOPp->reset) {
        __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v0 = 1U;
    } else {
        if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
                = (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                >> 9U));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((2U 
                                                 == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
                                                & (0U 
                                                   == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state)))
                                                ? ((IData)(1U) 
                                                   + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict))
                                                : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict))));
    if (vlTOPp->reset) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr = 0U;
    } else {
        if ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))) {
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr 
                = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found)
                    ? (vlTOPp->in_icache_pc_addr >> 
                       (0x1fU & (((0U >= (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index)) 
                                  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) 
                                     >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index))) 
                                 << 5U))) : 0U);
        }
    }
    if (vlTOPp->reset) {
        __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U;
    } else {
        if ((0x10000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
                = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U]);
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x20000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
                             << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
                                          >> 8U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x40000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
                             << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
                                          >> 0x10U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x80000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
                             << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
                                       >> 0x18U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x100000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
                = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U]);
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x200000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
                             << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
                                          >> 8U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x400000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
                             << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
                                          >> 0x10U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x800000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
                             << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
                                       >> 0x18U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x1000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
                = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U]);
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x2000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
                             << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
                                          >> 8U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x4000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
                             << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
                                          >> 0x10U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x8000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
                             << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
                                       >> 0x18U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x10000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
                = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U]);
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x20000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
                = (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
                            >> 8U));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x40000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
                = (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
                            >> 0x10U));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x80000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
                = (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
                            >> 0x18U));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
    }
    if (vlTOPp->reset) {
        __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U;
    } else {
        if ((1U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
                = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U]);
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((2U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
                             << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] 
                                          >> 8U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((4U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
                             << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] 
                                          >> 0x10U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((8U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
                             << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] 
                                       >> 0x18U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x10U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
                = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U]);
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x20U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
                             << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
                                          >> 8U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x40U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
                             << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
                                          >> 0x10U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
                             << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
                                       >> 0x18U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x100U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
                = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U]);
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x200U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
                             << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
                                          >> 8U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x400U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
                = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
                             << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
                                          >> 0x10U)));
            __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U;
            __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
            __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
        }
        if ((0x800U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
            __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 
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                = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                            >> 4U));
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        if ((0x1000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
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        if ((0x2000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
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    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid 
        = ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((2U 
                                                 == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                                                & (0U 
                                                   == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state)))
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    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid 
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    if (vlTOPp->reset) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr = 0U;
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        if ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))) {
            vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr 
                = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found)
                    ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
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                          >> (7U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index) 
                                    << 1U))))] : 0U);
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    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v0) {
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        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1U] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2U] = 0U;
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        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6U] = 0U;
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        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8U] = 0U;
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        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U;
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        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U;
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        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U;
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U;
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        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
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    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) {
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            = __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32;
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    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v0) {
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        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[5U] = 0U;
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                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46);
    }
    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), 
                          vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
                          [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47);
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state 
        = ((IData)(vlTOPp->reset) ? 0U : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state 
        = ((IData)(vlTOPp->reset) ? 0U : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state));
}

VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_combo__TOP__5\n"); );
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Variables
    WData/*31:0*/ __Vtemp132[4];
    WData/*31:0*/ __Vtemp133[4];
    WData/*31:0*/ __Vtemp134[4];
    WData/*31:0*/ __Vtemp135[4];
    // Body
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
        = vlTOPp->in_dcache_in_address[0U];
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
        = vlTOPp->in_dcache_in_address[1U];
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
        = vlTOPp->in_dcache_in_address[2U];
    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
        = vlTOPp->in_dcache_in_address[3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid)
            ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid)
            : (IData)(vlTOPp->in_icache_valid_pc_addr));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid 
        = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) 
           & VL_NEGATE_I((IData)((0xffU == (0xffU & 
                                            ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                              << 8U) 
                                             | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                                >> 0x18U)))))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid 
        = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) 
           & VL_NEGATE_I((IData)((0xffU != (0xffU & 
                                            ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                              << 8U) 
                                             | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                                >> 0x18U)))))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))
            ? (IData)(vlTOPp->in_dcache_mem_read) : 7U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))
            ? (IData)(vlTOPp->in_dcache_mem_write) : 7U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid 
        = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) 
           | (1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid 
        = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) 
           | (2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid 
        = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) 
           | (4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid 
        = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) 
           | (8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write 
        = ((7U != (IData)(vlTOPp->in_dcache_mem_write)) 
           & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))
            ? (IData)(vlTOPp->in_dcache_mem_write) : 7U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))
            ? (IData)(vlTOPp->in_dcache_mem_read) : 7U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid 
        = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid))
            ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)
            : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 0U;
    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 1U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = 0U;
    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = 0U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid 
        = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
            ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)
            : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks 
        = (((~ ((IData)(1U) << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]))) 
            & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) 
           | ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid)) 
              << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U])));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) 
                                        + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]))))) 
            & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) 
           | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) 
                     >> 1U)) << (0xfU & ((IData)(1U) 
                                         + (0xcU & 
                                            vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U])))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) 
                                        + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U]))))) 
            & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) 
           | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) 
                     >> 2U)) << (0xfU & ((IData)(2U) 
                                         + (0xcU & 
                                            vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U])))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) 
                                        + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U]))))) 
            & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) 
           | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) 
                     >> 3U)) << (0xfU & ((IData)(3U) 
                                         + (0xcU & 
                                            vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U])))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in 
        = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
           | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
                  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
              & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
                 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
        = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
            : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
                ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
                : (vlTOPp->in_icache_pc_addr >> (0x1fU 
                                                 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) 
                                                    << 5U)))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfffeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
              & (0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                               << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                            >> 2U))))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfffdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffffffeU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                             & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                               << 0x1eU) 
                                              | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                                 >> 2U)))) 
                                << 1U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfffbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffffffcU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                             & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                               << 0x1eU) 
                                              | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                 >> 2U)))) 
                                << 2U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfff7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffffff8U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                             & ((0U == (3U & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                              >> 2U))) 
                                << 3U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xffefU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
               & (1U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                             >> 2U))))) 
              << 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xffdfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffffffe0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 4U) & ((1U == (3U 
                                                & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                    << 0x1eU) 
                                                   | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                                      >> 2U)))) 
                                        << 5U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xffbfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffffffc0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 4U) & ((1U == (3U 
                                                & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                    << 0x1eU) 
                                                   | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                      >> 2U)))) 
                                        << 6U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xff7fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffffff80U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 4U) & ((1U == (3U 
                                                & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                   >> 2U))) 
                                        << 7U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfeffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
               & (2U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                             >> 2U))))) 
              << 8U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfdffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffffe00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 8U) & ((2U == (3U 
                                                & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                    << 0x1eU) 
                                                   | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                                      >> 2U)))) 
                                        << 9U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xfbffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffffc00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 8U) & ((2U == (3U 
                                                & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                    << 0x1eU) 
                                                   | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                      >> 2U)))) 
                                        << 0xaU))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xf7ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xfffff800U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 8U) & ((2U == (3U 
                                                & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                   >> 2U))) 
                                        << 0xbU))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xefffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
               & (3U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
                                             >> 2U))))) 
              << 0xcU));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xdfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffffe000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 0xcU) & ((3U == (3U 
                                                  & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                      << 0x1eU) 
                                                     | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
                                                        >> 2U)))) 
                                          << 0xdU))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0xbfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffffc000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 0xcU) & ((3U == (3U 
                                                  & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                      << 0x1eU) 
                                                     | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] 
                                                        >> 2U)))) 
                                          << 0xeU))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
        = ((0x7fffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
           | (0xffff8000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) 
                              << 0xcU) & ((3U == (3U 
                                                  & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
                                                     >> 2U))) 
                                          << 0xfU))));
    vlTOPp->__Vtableidx6 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index 
        = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index
        [vlTOPp->__Vtableidx6];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found 
        = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found
        [vlTOPp->__Vtableidx6];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i 
        = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i
        [vlTOPp->__Vtableidx6];
    vlTOPp->__Vtableidx7 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) 
                                    >> 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index 
        = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index
        [vlTOPp->__Vtableidx7];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found 
        = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found
        [vlTOPp->__Vtableidx7];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i 
        = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i
        [vlTOPp->__Vtableidx7];
    vlTOPp->__Vtableidx8 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) 
                                    >> 8U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index 
        = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index
        [vlTOPp->__Vtableidx8];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found 
        = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found
        [vlTOPp->__Vtableidx8];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i 
        = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i
        [vlTOPp->__Vtableidx8];
    vlTOPp->__Vtableidx9 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) 
                                    >> 0xcU));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index 
        = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index
        [vlTOPp->__Vtableidx9];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found 
        = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found
        [vlTOPp->__Vtableidx9];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i 
        = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i
        [vlTOPp->__Vtableidx9];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem 
        = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
           & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access 
        = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
           & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__sb_mask 
        = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
            ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
                     ? 2U : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
                              ? 4U : 8U)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[0U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[1U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[2U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[3U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[4U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[5U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[6U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[7U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
        [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                   >> 4U))][3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
        = ((VL_ULL(0x3fffff800000) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) 
           | (IData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
                             [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                        >> 4U))])));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
        = ((VL_ULL(0x7fffff) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) 
           | ((QData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
                              [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                         >> 4U))])) 
              << 0x17U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) 
           | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
           [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                      >> 4U))]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) 
           | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
              [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                         >> 4U))] << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = 0U;
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
    }
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
    }
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids = 0U;
    if ((0x80U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)));
    }
    if ((0x40U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)));
    }
    if ((0x20U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)));
    }
    if ((0x10U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)));
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids = 0U;
    if ((0x800U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)));
    }
    if ((0x400U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)));
    }
    if ((0x200U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)));
    }
    if ((0x100U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)));
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids = 0U;
    if ((0x8000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)));
    }
    if ((0x4000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)));
    }
    if ((0x2000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)));
    }
    if ((0x1000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids 
            = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)));
    }
    vlTOPp->__Vtableidx1 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index 
        = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index
        [vlTOPp->__Vtableidx1];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found 
        = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found
        [vlTOPp->__Vtableidx1];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i 
        = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i
        [vlTOPp->__Vtableidx1];
    vlTOPp->__Vtableidx2 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) 
                                    >> 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index 
        = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index
        [vlTOPp->__Vtableidx2];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found 
        = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found
        [vlTOPp->__Vtableidx2];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i 
        = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i
        [vlTOPp->__Vtableidx2];
    vlTOPp->__Vtableidx3 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) 
                                    >> 8U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index 
        = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index
        [vlTOPp->__Vtableidx3];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found 
        = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found
        [vlTOPp->__Vtableidx3];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i 
        = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i
        [vlTOPp->__Vtableidx3];
    vlTOPp->__Vtableidx4 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) 
                                    >> 0xcU));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index 
        = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index
        [vlTOPp->__Vtableidx4];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found 
        = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found
        [vlTOPp->__Vtableidx4];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i 
        = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i
        [vlTOPp->__Vtableidx4];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank 
        = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) 
           | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank 
        = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found)
               ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index)))
               : 0U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank 
        = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) 
           | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank 
        = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank 
        = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found)
                ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index)))
                : 0U) << 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank 
        = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank 
        = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank 
        = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found)
                ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index)))
                : 0U) << 8U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank 
        = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index) 
              << 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank 
        = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found) 
              << 3U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank 
        = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found)
                ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index)))
                : 0U) << 0xcU));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank 
        = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index) 
              << 6U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
            ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0U]
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
            ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[1U]
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
            ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[2U]
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
            ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[3U]
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
        = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
               ? 0xfU : 0U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
        = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
                ? 0xfU : 0U) << 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
        = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
                ? 0xfU : 0U) << 8U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
        = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
                ? 0xfU : 0U) << 0xcU));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) 
           | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 0U;
    if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
                  >> 1U)))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U;
    }
    if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U;
    if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
                  >> 1U)))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 1U;
    }
    if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
               & ((0x7fffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way)) 
                  == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                   >> 9U)))) ? 1U : 0U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) 
           | (((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
                 >> 1U) & ((0x7fffffU & (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
                                                 >> 0x17U))) 
                           == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                            >> 9U))))
                ? 1U : 0U) << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid 
        = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
           | (1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid 
        = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
           | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid 
        = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
           | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid 
        = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
           | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)) 
              << 3U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num 
        = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) 
           | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid 
        = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) 
           | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num 
        = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid 
        = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num 
        = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index) 
              << 4U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid 
        = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found) 
              << 2U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num 
        = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index) 
              << 6U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid 
        = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found) 
              << 3U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in 
        = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) 
           | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                  & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) 
              & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in 
        = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) 
           | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                  & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) 
              & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
                    >> 1U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in 
        = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) 
           | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                  & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) 
              & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
                    >> 2U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in 
        = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) 
           | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                  & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) 
              & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
                 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
                    >> 3U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
        = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
            : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
                ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
                : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
               (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
        = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
            : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
                ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
                : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
               (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
                      >> 2U))]));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
        = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
            : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
                ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
                : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
               (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
                      >> 4U))]));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
        = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
            : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
                ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr
                : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
               (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
                      >> 6U))]));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U];
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
    }
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U;
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 1U;
    }
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) 
           | ((IData)(1U) << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) 
           | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                    >> 2U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) 
           | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                    >> 4U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) 
           | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                    >> 6U))));
    __Vtemp132[0U] = 0U;
    __Vtemp132[1U] = 0U;
    __Vtemp132[2U] = 0U;
    __Vtemp132[3U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U] 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
            ? __Vtemp132[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))]
            : 0U);
    __Vtemp133[0U] = 0U;
    __Vtemp133[1U] = 0U;
    __Vtemp133[2U] = 0U;
    __Vtemp133[3U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U] 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
            ? __Vtemp133[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                >> 2U))] : 0U);
    __Vtemp134[0U] = 0U;
    __Vtemp134[1U] = 0U;
    __Vtemp134[2U] = 0U;
    __Vtemp134[3U] = 0U;
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                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
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                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we 
                                = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) 
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        if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
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            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we 
                                = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) 
                                   | (0xc0U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
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    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU] = 0U;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU] = 0U;
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                            VL_ASSIGNSEL_WIII(32,(0x60U 
                                                  & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
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        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
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                            VL_ASSIGNSEL_WIII(32,(0x1ffU 
                                                  & ((IData)(0x80U) 
                                                     + 
                                                     (0x60U 
                                                      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
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    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
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                            VL_ASSIGNSEL_WIII(32,(0x1ffU 
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                                                     + 
                                                     (0x60U 
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                            VL_ASSIGNSEL_WIII(32,(0x1ffU 
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                                                     + 
                                                     (0x60U 
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                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid 
                                    = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) 
                                       | ((IData)(1U) 
                                          << (3U & 
                                              ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                               >> 3U))));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid 
                                    = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) 
                                       | ((IData)(1U) 
                                          << (3U & 
                                              ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                               >> 6U))));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                >> 0x18U)))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid 
                                    = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) 
                                       | ((IData)(1U) 
                                          << (3U & 
                                              ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                               >> 9U))));
                            }
                        }
                    }
                }
            }
        }
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = 0U;
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 
                                = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                             << 0x1aU) 
                                            | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                               >> 6U)));
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                = ((0xfffff80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                   | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1));
                        }
                    }
                }
            } else {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 
                                    = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                 << 0x1aU) 
                                                | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                                   >> 6U)));
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                    = ((0xfffff80U 
                                        & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                       | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 
                                = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                             << 0x1aU) 
                                            | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                               >> 6U)));
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                = ((0xfffc07fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) 
                                      << 7U));
                        }
                    }
                }
            } else {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 
                                    = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                 << 0x1aU) 
                                                | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                   >> 6U)));
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                    = ((0xfffc07fU 
                                        & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                       | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) 
                                          << 7U));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                           >> 0x18U))))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 
                                = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                             << 0x1aU) 
                                            | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                               >> 6U)));
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                = ((0xfe03fffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) 
                                      << 0xeU));
                        }
                    }
                }
            } else {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 
                                    = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                 << 0x1aU) 
                                                | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                   >> 6U)));
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                    = ((0xfe03fffU 
                                        & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                       | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) 
                                          << 0xeU));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                >> 0x18U)))) {
            if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                    if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                        if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 
                                = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                            >> 6U));
                            vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) 
                                      << 0x15U));
                        }
                    }
                }
            } else {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 
                                    = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                >> 6U));
                                vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                                    = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) 
                                       | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) 
                                          << 0x15U));
                            }
                        }
                    }
                }
            }
        }
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way 
        = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) 
              & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
        = ((0xffff0000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) 
           | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)
               ? 0U : (0xffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way 
        = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) 
               & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)) 
              << 1U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
        = ((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) 
           | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)
                ? (0xffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we))
                : 0U) << 0x10U));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual 
        = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) 
            | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))
            ? (((0U == (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                  << 7U) + (0x60U & 
                                            (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                             << 3U)))))
                 ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                         ((IData)(1U) + (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                 << 7U) 
                                                + (0x60U 
                                                   & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                      << 3U))) 
                                               >> 5U)))] 
                         << ((IData)(0x20U) - (0x1fU 
                                               & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                   << 7U) 
                                                  + 
                                                  (0x60U 
                                                   & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                      << 3U))))))) 
               | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                  (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                           << 7U) + (0x60U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                              << 3U))) 
                         >> 5U))] >> (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                << 7U) 
                                               + (0x60U 
                                                  & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                     << 3U))))))
            : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
                ? ((((0U == (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                       << 7U) + (0x60U 
                                                 & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                    << 3U)))))
                      ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                              ((IData)(1U) + (7U & 
                                              ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                 << 7U) 
                                                + (0x60U 
                                                   & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                      << 3U))) 
                                               >> 5U)))] 
                              << ((IData)(0x20U) - 
                                  (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                             << 7U) 
                                            + (0x60U 
                                               & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                  << 3U))))))) 
                    | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                       (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                << 7U) + (0x60U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                   << 3U))) 
                              >> 5U))] >> (0x1fU & 
                                           (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                             << 7U) 
                                            + (0x60U 
                                               & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                  << 3U)))))) 
                   >> 8U) : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
                              ? ((((0U == (0x1fU & 
                                           (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                             << 7U) 
                                            + (0x60U 
                                               & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                  << 3U)))))
                                    ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                                            ((IData)(1U) 
                                             + (7U 
                                                & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                     << 7U) 
                                                    + 
                                                    (0x60U 
                                                     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                        << 3U))) 
                                                   >> 5U)))] 
                                            << ((IData)(0x20U) 
                                                - (0x1fU 
                                                   & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                       << 7U) 
                                                      + 
                                                      (0x60U 
                                                       & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                          << 3U))))))) 
                                  | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                                     (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                              << 7U) 
                                             + (0x60U 
                                                & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                   << 3U))) 
                                            >> 5U))] 
                                     >> (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                   << 7U) 
                                                  + 
                                                  (0x60U 
                                                   & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                      << 3U)))))) 
                                 >> 0x10U) : ((((0U 
                                                 == 
                                                 (0x1fU 
                                                  & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                      << 7U) 
                                                     + 
                                                     (0x60U 
                                                      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                         << 3U)))))
                                                 ? 0U
                                                 : 
                                                (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                                                 ((IData)(1U) 
                                                  + 
                                                  (7U 
                                                   & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                        << 7U) 
                                                       + 
                                                       (0x60U 
                                                        & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                           << 3U))) 
                                                      >> 5U)))] 
                                                 << 
                                                 ((IData)(0x20U) 
                                                  - 
                                                  (0x1fU 
                                                   & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                       << 7U) 
                                                      + 
                                                      (0x60U 
                                                       & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                          << 3U))))))) 
                                               | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
                                                  (7U 
                                                   & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                        << 7U) 
                                                       + 
                                                       (0x60U 
                                                        & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                           << 3U))) 
                                                      >> 5U))] 
                                                  >> 
                                                  (0x1fU 
                                                   & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
                                                       << 7U) 
                                                      + 
                                                      (0x60U 
                                                       & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                                          << 3U)))))) 
                                              >> 0x18U))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
        = ((0x2dU >= (0x3fU & ((IData)(0x17U) * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))
            ? (0x7fffffU & (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
                                    >> (0x3fU & ((IData)(0x17U) 
                                                 * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))))
            : 0U);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use 
        = (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
                 >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests 
        = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
            ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
               & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))
            : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) 
               & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[1U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[2U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[3U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[4U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 7U))][0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[5U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 7U))][1U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[6U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 7U))][2U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[7U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 7U))][3U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[8U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0xeU))][0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[9U] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0xeU))][1U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xaU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0xeU))][2U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xbU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0xeU))][3U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xcU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0x15U))][0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xdU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0x15U))][1U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xeU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0x15U))][2U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xfU] 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
            ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
           [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
                      >> 0x15U))][3U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank 
        = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) 
            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
               == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
                                >> 9U)))) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use));
    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                VL_ASSIGNSEL_WIII(32,
                                                  (0x60U 
                                                   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                                      << 5U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, 
                                                  vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                  (3U 
                                                   & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
                                                      >> 4U))]);
                            }
                        }
                    }
                }
            }
        }
    }
    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                VL_ASSIGNSEL_WIII(32,
                                                  (0x60U 
                                                   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                                      << 2U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, 
                                                  (((0U 
                                                     == 
                                                     (0x1fU 
                                                      & ((IData)(0x80U) 
                                                         + 
                                                         (0x60U 
                                                          & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                             << 1U)))))
                                                     ? 0U
                                                     : 
                                                    (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                     ((IData)(1U) 
                                                      + 
                                                      (0xfU 
                                                       & (((IData)(0x80U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                               << 1U))) 
                                                          >> 5U)))] 
                                                     << 
                                                     ((IData)(0x20U) 
                                                      - 
                                                      (0x1fU 
                                                       & ((IData)(0x80U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                              << 1U))))))) 
                                                   | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                      (0xfU 
                                                       & (((IData)(0x80U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                               << 1U))) 
                                                          >> 5U))] 
                                                      >> 
                                                      (0x1fU 
                                                       & ((IData)(0x80U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] 
                                                              << 1U)))))));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                 << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                           >> 0x18U))))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                VL_ASSIGNSEL_WIII(32,
                                                  (0x60U 
                                                   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                                      >> 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, 
                                                  (((0U 
                                                     == 
                                                     (0x1fU 
                                                      & ((IData)(0x100U) 
                                                         + 
                                                         (0x60U 
                                                          & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                             << 1U)))))
                                                     ? 0U
                                                     : 
                                                    (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                     ((IData)(1U) 
                                                      + 
                                                      (0xfU 
                                                       & (((IData)(0x100U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                               << 1U))) 
                                                          >> 5U)))] 
                                                     << 
                                                     ((IData)(0x20U) 
                                                      - 
                                                      (0x1fU 
                                                       & ((IData)(0x100U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                              << 1U))))))) 
                                                   | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                      (0xfU 
                                                       & (((IData)(0x100U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                               << 1U))) 
                                                          >> 5U))] 
                                                      >> 
                                                      (0x1fU 
                                                       & ((IData)(0x100U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] 
                                                              << 1U)))))));
                            }
                        }
                    }
                }
            }
        }
    }
    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) {
        if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                >> 0x18U)))) {
            if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) {
                if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                    if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                        if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                            if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) {
                                VL_ASSIGNSEL_WIII(32,
                                                  (0x60U 
                                                   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
                                                      >> 4U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, 
                                                  (((0U 
                                                     == 
                                                     (0x1fU 
                                                      & ((IData)(0x180U) 
                                                         + 
                                                         (0x60U 
                                                          & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                             << 1U)))))
                                                     ? 0U
                                                     : 
                                                    (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                     ((IData)(1U) 
                                                      + 
                                                      (0xfU 
                                                       & (((IData)(0x180U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                               << 1U))) 
                                                          >> 5U)))] 
                                                     << 
                                                     ((IData)(0x20U) 
                                                      - 
                                                      (0x1fU 
                                                       & ((IData)(0x180U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                              << 1U))))))) 
                                                   | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[
                                                      (0xfU 
                                                       & (((IData)(0x180U) 
                                                           + 
                                                           (0x60U 
                                                            & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                               << 1U))) 
                                                          >> 5U))] 
                                                      >> 
                                                      (0x1fU 
                                                       & ((IData)(0x180U) 
                                                          + 
                                                          (0x60U 
                                                           & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] 
                                                              << 1U)))))));
                            }
                        }
                    }
                }
            }
        }
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = 0U;
    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read 
            = (((~ ((IData)(0xffffffffU) << (0x1fU 
                                             & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) 
                                                << 5U)))) 
                & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read) 
               | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)
                    ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
                        ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                            ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                            : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
                        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
                            ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                                ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                                : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
                            : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
                                ? (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                                : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
                                    ? (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
                                    : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))
                    : 0U) << (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) 
                                       << 5U))));
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
           & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0U] 
        = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank;
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 0U;
    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 1U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U;
    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) {
        vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U;
    }
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state 
        = (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
            & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss))
            ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
                     ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
                              & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))
                              ? 2U : 0U)));
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank 
        = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)
             ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index))
             : 0U) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask
           [0U]);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)
            ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read
            : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read);
    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid 
        = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) 
           & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)));
    vlTOPp->out_icache_stall = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) 
                                | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)));
}

void Vcache_simX::_eval(Vcache_simX__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_eval\n"); );
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->_combo__TOP__1(vlSymsp);
    vlTOPp->__Vm_traceActivity = (2U | vlTOPp->__Vm_traceActivity);
    if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) 
         | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
        vlTOPp->_sequent__TOP__4(vlSymsp);
        vlTOPp->__Vm_traceActivity = (4U | vlTOPp->__Vm_traceActivity);
        vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(vlSymsp);
        vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(vlSymsp);
        vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(vlSymsp);
        vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(vlSymsp);
    }
    vlTOPp->_combo__TOP__5(vlSymsp);
    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(vlSymsp);
    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(vlSymsp);
    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(vlSymsp);
    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(vlSymsp);
    vlTOPp->_settle__TOP__3(vlSymsp);
    // Final
    vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
    vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset;
}

void Vcache_simX::_eval_initial(Vcache_simX__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_eval_initial\n"); );
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
    vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset;
}

void Vcache_simX::final() {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::final\n"); );
    // Variables
    Vcache_simX__Syms* __restrict vlSymsp = this->__VlSymsp;
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}

void Vcache_simX::_eval_settle(Vcache_simX__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_eval_settle\n"); );
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->_settle__TOP__2(vlSymsp);
    vlTOPp->__Vm_traceActivity = (1U | vlTOPp->__Vm_traceActivity);
    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(vlSymsp);
    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(vlSymsp);
    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(vlSymsp);
    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(vlSymsp);
    vlTOPp->_settle__TOP__3(vlSymsp);
}

VL_INLINE_OPT QData Vcache_simX::_change_request(Vcache_simX__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_change_request\n"); );
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    // Change detection
    QData __req = false;  // Logically a bool
    return __req;
}

#ifdef VL_DEBUG
void Vcache_simX::_eval_debug_assertions() {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_eval_debug_assertions\n"); );
    // Body
    if (VL_UNLIKELY((clk & 0xfeU))) {
        Verilated::overWidthError("clk");}
    if (VL_UNLIKELY((reset & 0xfeU))) {
        Verilated::overWidthError("reset");}
    if (VL_UNLIKELY((in_icache_valid_pc_addr & 0xfeU))) {
        Verilated::overWidthError("in_icache_valid_pc_addr");}
    if (VL_UNLIKELY((in_dcache_mem_read & 0xf8U))) {
        Verilated::overWidthError("in_dcache_mem_read");}
    if (VL_UNLIKELY((in_dcache_mem_write & 0xf8U))) {
        Verilated::overWidthError("in_dcache_mem_write");}
}
#endif // VL_DEBUG

void Vcache_simX::_ctor_var_reset() {
    VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_ctor_var_reset\n"); );
    // Body
    clk = VL_RAND_RESET_I(1);
    reset = VL_RAND_RESET_I(1);
    in_icache_pc_addr = VL_RAND_RESET_I(32);
    in_icache_valid_pc_addr = VL_RAND_RESET_I(1);
    out_icache_stall = VL_RAND_RESET_I(1);
    in_dcache_mem_read = VL_RAND_RESET_I(3);
    in_dcache_mem_write = VL_RAND_RESET_I(3);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            in_dcache_in_valid[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            in_dcache_in_address[__Vi0] = VL_RAND_RESET_I(32);
    }}
    out_dcache_stall = VL_RAND_RESET_I(1);
    cache_simX__DOT__icache_i_m_ready = VL_RAND_RESET_I(1);
    cache_simX__DOT__dcache_i_m_ready = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__read_or_write = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read = VL_RAND_RESET_I(3);
    cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write = VL_RAND_RESET_I(3);
    cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read = VL_RAND_RESET_I(3);
    cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write = VL_RAND_RESET_I(3);
    cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read = VL_RAND_RESET_I(3);
    VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid = VL_RAND_RESET_I(4);
    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = VL_RAND_RESET_I(28);
    VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata);
    VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we = VL_RAND_RESET_I(8);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid = VL_RAND_RESET_I(4);
    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data);
    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 = VL_RAND_RESET_I(7);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 = VL_RAND_RESET_I(7);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids = VL_RAND_RESET_I(16);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num = VL_RAND_RESET_I(8);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = VL_RAND_RESET_I(3);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids = VL_RAND_RESET_I(3);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids = VL_RAND_RESET_I(3);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids = VL_RAND_RESET_I(3);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    { int __Vi0=0; for (; __Vi0<128; ++__Vi0) {
            VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]);
    }}
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32);
    { int __Vi0=0; for (; __Vi0<128; ++__Vi0) {
            VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]);
    }}
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32);
    { int __Vi0=0; for (; __Vi0<128; ++__Vi0) {
            VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]);
    }}
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32);
    { int __Vi0=0; for (; __Vi0<128; ++__Vi0) {
            VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]);
    }}
    cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32);
    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read);
    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read);
    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank = VL_RAND_RESET_I(8);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank = VL_RAND_RESET_I(16);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid = VL_RAND_RESET_I(4);
    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks = VL_RAND_RESET_I(16);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual = VL_RAND_RESET_I(4);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[__Vi0] = VL_RAND_RESET_I(4);
    }}
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__state = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[__Vi0] = VL_RAND_RESET_I(1);
    }}
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use = VL_RAND_RESET_I(23);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__sb_mask = VL_RAND_RESET_I(4);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way = VL_RAND_RESET_Q(46);
    VL_RAND_RESET_W(256,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way = VL_RAND_RESET_I(32);
    VL_RAND_RESET_W(256,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way = VL_RAND_RESET_I(2);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use = VL_RAND_RESET_I(1);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
            VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[__Vi0]);
    }}
    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
            cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(23);
    }}
    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
            cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
            cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1);
    }}
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32);
    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
            VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[__Vi0]);
    }}
    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
            cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(23);
    }}
    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
            cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
            cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1);
    }}
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32);
    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32);
    __Vtableidx1 = 0;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[0] = 0U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[1] = 0U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[2] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[3] = 0U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[4] = 2U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[5] = 0U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[6] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[7] = 0U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[8] = 3U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[9] = 0U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[10] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[11] = 0U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[12] = 2U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[13] = 0U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[14] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[15] = 0U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[0] = 0U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[1] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[2] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[3] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[4] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[5] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[6] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[7] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[8] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[9] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[10] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[11] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[12] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[13] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[14] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[15] = 1U;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx2 = 0;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[0] = 0U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[1] = 0U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[2] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[3] = 0U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[4] = 2U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[5] = 0U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[6] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[7] = 0U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[8] = 3U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[9] = 0U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[10] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[11] = 0U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[12] = 2U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[13] = 0U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[14] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[15] = 0U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[0] = 0U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[1] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[2] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[3] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[4] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[5] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[6] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[7] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[8] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[9] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[10] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[11] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[12] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[13] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[14] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[15] = 1U;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx3 = 0;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[0] = 0U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[1] = 0U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[2] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[3] = 0U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[4] = 2U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[5] = 0U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[6] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[7] = 0U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[8] = 3U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[9] = 0U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[10] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[11] = 0U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[12] = 2U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[13] = 0U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[14] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[15] = 0U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[0] = 0U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[1] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[2] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[3] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[4] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[5] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[6] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[7] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[8] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[9] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[10] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[11] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[12] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[13] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[14] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[15] = 1U;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx4 = 0;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[0] = 0U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[1] = 0U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[2] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[3] = 0U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[4] = 2U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[5] = 0U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[6] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[7] = 0U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[8] = 3U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[9] = 0U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[10] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[11] = 0U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[12] = 2U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[13] = 0U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[14] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[15] = 0U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[0] = 0U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[1] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[2] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[3] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[4] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[5] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[6] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[7] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[8] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[9] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[10] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[11] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[12] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[13] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[14] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[15] = 1U;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx5 = 0;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[0] = 0U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[1] = 0U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[2] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[3] = 0U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[4] = 2U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[5] = 0U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[6] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[7] = 0U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[8] = 3U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[9] = 0U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[10] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[11] = 0U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[12] = 2U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[13] = 0U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[14] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[15] = 0U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[0] = 0U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[1] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[2] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[3] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[4] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[5] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[6] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[7] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[8] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[9] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[10] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[11] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[12] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[13] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[14] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[15] = 1U;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[0] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[1] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[2] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[3] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[4] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[5] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[6] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[7] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[8] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[9] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[10] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[11] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[12] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[13] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[14] = 0xffffffffU;
    __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[15] = 0xffffffffU;
    __Vtableidx6 = 0;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[0] = 0U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[1] = 0U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[2] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[3] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[4] = 2U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[5] = 2U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[6] = 2U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[7] = 2U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[8] = 3U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[9] = 3U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[10] = 3U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[11] = 3U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[12] = 3U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[13] = 3U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[14] = 3U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[15] = 3U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[0] = 0U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[1] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[2] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[3] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[4] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[5] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[6] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[7] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[8] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[9] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[10] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[11] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[12] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[13] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[14] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[15] = 1U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[0] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[1] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[2] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[3] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[4] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[5] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[6] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[7] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[8] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[9] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[10] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[11] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[12] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[13] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[14] = 4U;
    __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[15] = 4U;
    __Vtableidx7 = 0;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[0] = 0U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[1] = 0U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[2] = 1U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[3] = 1U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[4] = 2U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[5] = 2U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[6] = 2U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[7] = 2U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[8] = 3U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[9] = 3U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[10] = 3U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[11] = 3U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[12] = 3U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[13] = 3U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[14] = 3U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[15] = 3U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[0] = 0U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[1] = 1U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[2] = 1U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[3] = 1U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[4] = 1U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[5] = 1U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[6] = 1U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[7] = 1U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[8] = 1U;
    __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[9] = 1U;
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}