// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVX_cache.h for the primary calling header

#include "VVX_cache.h"
#include "VVX_cache__Syms.h"

//==========
CData/*1:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[16];
CData/*0:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[16];
IData/*31:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
CData/*1:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[16];
CData/*0:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16];
IData/*31:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
CData/*1:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16];
CData/*0:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[16];
IData/*31:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
CData/*1:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16];
CData/*0:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16];
IData/*31:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
CData/*1:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
CData/*0:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
IData/*31:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
CData/*1:0*/ VVX_cache::__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
CData/*0:0*/ VVX_cache::__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
IData/*31:0*/ VVX_cache::__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
CData/*1:0*/ VVX_cache::__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
CData/*0:0*/ VVX_cache::__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
IData/*31:0*/ VVX_cache::__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
CData/*1:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
CData/*0:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
IData/*31:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];

VL_CTOR_IMP(VVX_cache) {
    VVX_cache__Syms* __restrict vlSymsp = __VlSymsp = new VVX_cache__Syms(this, name());
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Reset internal values
    
    // Reset structure values
    _ctor_var_reset();
}

void VVX_cache::__Vconfigure(VVX_cache__Syms* vlSymsp, bool first) {
    if (0 && first) {}  // Prevent unused
    this->__VlSymsp = vlSymsp;
}

VVX_cache::~VVX_cache() {
    delete __VlSymsp; __VlSymsp=NULL;
}

void VVX_cache::eval_step() {
    VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_cache::eval\n"); );
    VVX_cache__Syms* __restrict vlSymsp = this->__VlSymsp;  // Setup global symbol table
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
    // Debug assertions
    _eval_debug_assertions();
#endif  // VL_DEBUG
    // Initialize
    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
#ifdef VM_TRACE
    // Tracing
#endif  // VM_TRACE
    // Evaluate till stable
    int __VclockLoop = 0;
    QData __Vchange = 1;
    do {
        VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
        vlSymsp->__Vm_activity = true;
        _eval(vlSymsp);
        if (VL_UNLIKELY(++__VclockLoop > 100)) {
            // About to fail, so enable debug to see what's not settling.
            // Note you must run make with OPT=-DVL_DEBUG for debug prints.
            int __Vsaved_debug = Verilated::debug();
            Verilated::debug(1);
            __Vchange = _change_request(vlSymsp);
            Verilated::debug(__Vsaved_debug);
            VL_FATAL_MT("../../rtl/cache/VX_cache.v", 3, "",
                "Verilated model didn't converge\n"
                "- See DIDNOTCONVERGE in the Verilator manual");
        } else {
            __Vchange = _change_request(vlSymsp);
        }
    } while (VL_UNLIKELY(__Vchange));
}

void VVX_cache::_eval_initial_loop(VVX_cache__Syms* __restrict vlSymsp) {
    vlSymsp->__Vm_didInit = true;
    _eval_initial(vlSymsp);
    vlSymsp->__Vm_activity = true;
    // Evaluate till stable
    int __VclockLoop = 0;
    QData __Vchange = 1;
    do {
        _eval_settle(vlSymsp);
        _eval(vlSymsp);
        if (VL_UNLIKELY(++__VclockLoop > 100)) {
            // About to fail, so enable debug to see what's not settling.
            // Note you must run make with OPT=-DVL_DEBUG for debug prints.
            int __Vsaved_debug = Verilated::debug();
            Verilated::debug(1);
            __Vchange = _change_request(vlSymsp);
            Verilated::debug(__Vsaved_debug);
            VL_FATAL_MT("../../rtl/cache/VX_cache.v", 3, "",
                "Verilated model didn't DC converge\n"
                "- See DIDNOTCONVERGE in the Verilator manual");
        } else {
            __Vchange = _change_request(vlSymsp);
        }
    } while (VL_UNLIKELY(__Vchange));
}

void VVX_cache::_initial__TOP__1(VVX_cache__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_initial__TOP__1\n"); );
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->snp_fwdout_valid = 0U;
    vlTOPp->snp_fwdout_addr = VL_ULL(0);
    vlTOPp->snp_fwdout_invalidate = 0U;
    vlTOPp->snp_fwdout_tag = 0U;
    vlTOPp->snp_fwdin_ready = 0U;
}

VL_INLINE_OPT void VVX_cache::_combo__TOP__2(VVX_cache__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_combo__TOP__2\n"); );
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = 0U;
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid 
        = (((~ ((IData)(1U) << (0xcU & vlTOPp->core_req_addr[0U]))) 
            & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) 
           | ((1U & (IData)(vlTOPp->core_req_valid)) 
              << (0xcU & vlTOPp->core_req_addr[0U])));
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) 
                                        + (0xcU & (
                                                   vlTOPp->core_req_addr[1U] 
                                                   << 2U)))))) 
            & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) 
           | ((1U & ((IData)(vlTOPp->core_req_valid) 
                     >> 1U)) << (0xfU & ((IData)(1U) 
                                         + (0xcU & 
                                            (vlTOPp->core_req_addr[1U] 
                                             << 2U))))));
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) 
                                        + (0xcU & (
                                                   (vlTOPp->core_req_addr[2U] 
                                                    << 4U) 
                                                   | (0xcU 
                                                      & (vlTOPp->core_req_addr[1U] 
                                                         >> 0x1cU)))))))) 
            & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) 
           | ((1U & ((IData)(vlTOPp->core_req_valid) 
                     >> 2U)) << (0xfU & ((IData)(2U) 
                                         + (0xcU & 
                                            ((vlTOPp->core_req_addr[2U] 
                                              << 4U) 
                                             | (0xcU 
                                                & (vlTOPp->core_req_addr[1U] 
                                                   >> 0x1cU))))))));
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) 
                                        + (0xcU & (
                                                   (vlTOPp->core_req_addr[3U] 
                                                    << 6U) 
                                                   | (0x3cU 
                                                      & (vlTOPp->core_req_addr[2U] 
                                                         >> 0x1aU)))))))) 
            & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) 
           | ((1U & ((IData)(vlTOPp->core_req_valid) 
                     >> 3U)) << (0xfU & ((IData)(3U) 
                                         + (0xcU & 
                                            ((vlTOPp->core_req_addr[3U] 
                                              << 6U) 
                                             | (0x3cU 
                                                & (vlTOPp->core_req_addr[2U] 
                                                   >> 0x1aU))))))));
    vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = 0xfU;
    vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel 
        = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[1U] 
                                      << 0x1eU) | (
                                                   vlTOPp->core_req_addr[0U] 
                                                   >> 2U))))) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel));
    vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel 
        = ((~ ((IData)(1U) << (3U & vlTOPp->core_req_addr[1U]))) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel));
    vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel 
        = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[2U] 
                                      << 2U) | (vlTOPp->core_req_addr[1U] 
                                                >> 0x1eU))))) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel));
    vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel 
        = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[3U] 
                                      << 4U) | (vlTOPp->core_req_addr[2U] 
                                                >> 0x1cU))))) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel));
}

void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_settle__TOP__3\n"); );
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Variables
    WData/*191:0*/ __Vtemp146[6];
    WData/*255:0*/ __Vtemp147[8];
    WData/*191:0*/ __Vtemp160[6];
    WData/*255:0*/ __Vtemp161[8];
    WData/*191:0*/ __Vtemp174[6];
    WData/*255:0*/ __Vtemp175[8];
    WData/*191:0*/ __Vtemp188[6];
    WData/*255:0*/ __Vtemp189[8];
    WData/*127:0*/ __Vtemp191[4];
    WData/*287:0*/ __Vtemp198[9];
    WData/*287:0*/ __Vtemp199[9];
    WData/*319:0*/ __Vtemp201[10];
    WData/*127:0*/ __Vtemp204[4];
    WData/*287:0*/ __Vtemp211[9];
    WData/*287:0*/ __Vtemp212[9];
    WData/*319:0*/ __Vtemp214[10];
    WData/*127:0*/ __Vtemp217[4];
    WData/*287:0*/ __Vtemp224[9];
    WData/*287:0*/ __Vtemp225[9];
    WData/*319:0*/ __Vtemp227[10];
    WData/*127:0*/ __Vtemp230[4];
    WData/*287:0*/ __Vtemp237[9];
    WData/*287:0*/ __Vtemp238[9];
    WData/*319:0*/ __Vtemp240[10];
    // Body
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = 0U;
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid 
        = (((~ ((IData)(1U) << (0xcU & vlTOPp->core_req_addr[0U]))) 
            & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) 
           | ((1U & (IData)(vlTOPp->core_req_valid)) 
              << (0xcU & vlTOPp->core_req_addr[0U])));
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) 
                                        + (0xcU & (
                                                   vlTOPp->core_req_addr[1U] 
                                                   << 2U)))))) 
            & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) 
           | ((1U & ((IData)(vlTOPp->core_req_valid) 
                     >> 1U)) << (0xfU & ((IData)(1U) 
                                         + (0xcU & 
                                            (vlTOPp->core_req_addr[1U] 
                                             << 2U))))));
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) 
                                        + (0xcU & (
                                                   (vlTOPp->core_req_addr[2U] 
                                                    << 4U) 
                                                   | (0xcU 
                                                      & (vlTOPp->core_req_addr[1U] 
                                                         >> 0x1cU)))))))) 
            & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) 
           | ((1U & ((IData)(vlTOPp->core_req_valid) 
                     >> 2U)) << (0xfU & ((IData)(2U) 
                                         + (0xcU & 
                                            ((vlTOPp->core_req_addr[2U] 
                                              << 4U) 
                                             | (0xcU 
                                                & (vlTOPp->core_req_addr[1U] 
                                                   >> 0x1cU))))))));
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid 
        = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) 
                                        + (0xcU & (
                                                   (vlTOPp->core_req_addr[3U] 
                                                    << 6U) 
                                                   | (0x3cU 
                                                      & (vlTOPp->core_req_addr[2U] 
                                                         >> 0x1aU)))))))) 
            & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) 
           | ((1U & ((IData)(vlTOPp->core_req_valid) 
                     >> 3U)) << (0xfU & ((IData)(3U) 
                                         + (0xcU & 
                                            ((vlTOPp->core_req_addr[3U] 
                                              << 6U) 
                                             | (0x3cU 
                                                & (vlTOPp->core_req_addr[2U] 
                                                   >> 0x1aU))))))));
    vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = 0xfU;
    vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel 
        = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[1U] 
                                      << 0x1eU) | (
                                                   vlTOPp->core_req_addr[0U] 
                                                   >> 2U))))) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel));
    vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel 
        = ((~ ((IData)(1U) << (3U & vlTOPp->core_req_addr[1U]))) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel));
    vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel 
        = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[2U] 
                                      << 2U) | (vlTOPp->core_req_addr[1U] 
                                                >> 0x1eU))))) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel));
    vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel 
        = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[3U] 
                                      << 4U) | (vlTOPp->core_req_addr[2U] 
                                                >> 0x1cU))))) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] 
        = vlTOPp->dram_rsp_data[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] 
        = vlTOPp->dram_rsp_data[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] 
        = vlTOPp->dram_rsp_data[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] 
        = vlTOPp->dram_rsp_data[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] 
        = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] 
        = vlTOPp->dram_rsp_data[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] 
        = vlTOPp->dram_rsp_data[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] 
        = vlTOPp->dram_rsp_data[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] 
        = vlTOPp->dram_rsp_data[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] 
        = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] 
        = vlTOPp->dram_rsp_data[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] 
        = vlTOPp->dram_rsp_data[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] 
        = vlTOPp->dram_rsp_data[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] 
        = vlTOPp->dram_rsp_data[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] 
        = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] 
        = vlTOPp->dram_rsp_data[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] 
        = vlTOPp->dram_rsp_data[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] 
        = vlTOPp->dram_rsp_data[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] 
        = vlTOPp->dram_rsp_data[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] 
        = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in 
        = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr 
                                           >> 2U)))) 
            << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) 
                                          << 0x1cU) 
                                         | vlTOPp->snp_req_tag))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in 
        = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr 
                                           >> 2U)))) 
            << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) 
                                          << 0x1cU) 
                                         | vlTOPp->snp_req_tag))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in 
        = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr 
                                           >> 2U)))) 
            << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) 
                                          << 0x1cU) 
                                         | vlTOPp->snp_req_tag))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in 
        = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr 
                                           >> 2U)))) 
            << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) 
                                          << 0x1cU) 
                                         | vlTOPp->snp_req_tag))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing 
        = (((IData)(vlTOPp->snp_req_valid) & (0U == 
                                              (3U & vlTOPp->snp_req_addr))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing 
        = (((IData)(vlTOPp->dram_rsp_valid) & (0U == 
                                               (3U 
                                                & vlTOPp->dram_rsp_tag))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing 
        = (((IData)(vlTOPp->snp_req_valid) & (1U == 
                                              (3U & vlTOPp->snp_req_addr))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing 
        = (((IData)(vlTOPp->dram_rsp_valid) & (1U == 
                                               (3U 
                                                & vlTOPp->dram_rsp_tag))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing 
        = (((IData)(vlTOPp->snp_req_valid) & (2U == 
                                              (3U & vlTOPp->snp_req_addr))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing 
        = (((IData)(vlTOPp->dram_rsp_valid) & (2U == 
                                               (3U 
                                                & vlTOPp->dram_rsp_tag))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing 
        = (((IData)(vlTOPp->snp_req_valid) & (3U == 
                                              (3U & vlTOPp->snp_req_addr))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing 
        = (((IData)(vlTOPp->dram_rsp_valid) & (3U == 
                                               (3U 
                                                & vlTOPp->dram_rsp_tag))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use 
        = (((0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid)) 
            | (0U == ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid) 
                      - (IData)(1U)))) & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) 
           | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) 
           | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 1U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) 
           | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 2U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) 
           | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 3U)));
    vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = 
        ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) 
         | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))));
    vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = 
        ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) 
         | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                  << 1U)));
    vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = 
        ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) 
         | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                  << 2U)));
    vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = 
        ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) 
         | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                  << 3U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                 [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                 >> 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                 [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                 >> 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                 [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                 >> 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                 [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                 >> 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
            << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                        >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
            << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                        >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
            << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                        >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
            << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                        >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0U] 
        = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                  << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                              >> 0x12U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0U] 
        = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                  << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                              >> 0x12U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0U] 
        = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                  << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                              >> 0x12U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0U] 
        = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                  << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                              >> 0x12U)));
    vlTOPp->VX_cache__DOT__per_bank_core_req_ready 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) 
           | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))));
    vlTOPp->VX_cache__DOT__per_bank_core_req_ready 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) 
           | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 1U)));
    vlTOPp->VX_cache__DOT__per_bank_core_req_ready 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) 
           | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 2U)));
    vlTOPp->VX_cache__DOT__per_bank_core_req_ready 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) 
           | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 3U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0U] 
        = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)(
                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) 
                                       << 0x3fU) | 
                                      (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) 
                                        << 0x1fU) | 
                                       ((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) 
                                        >> 1U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0U] 
        = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)(
                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) 
                                       << 0x3fU) | 
                                      (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) 
                                        << 0x1fU) | 
                                       ((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) 
                                        >> 1U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0U] 
        = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)(
                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) 
                                       << 0x3fU) | 
                                      (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) 
                                        << 0x1fU) | 
                                       ((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) 
                                        >> 1U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0U] 
        = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)(
                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) 
                                       << 0x3fU) | 
                                      (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) 
                                        << 0x1fU) | 
                                       ((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) 
                                        >> 1U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->__Vtableidx5 = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index 
        = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index
        [vlTOPp->__Vtableidx5];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request 
        = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request
        [vlTOPp->__Vtableidx5];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx5];
    vlTOPp->__Vtableidx6 = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index 
        = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index
        [vlTOPp->__Vtableidx6];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request 
        = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request
        [vlTOPp->__Vtableidx6];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx6];
    vlTOPp->__Vtableidx7 = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index 
        = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index
        [vlTOPp->__Vtableidx7];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request 
        = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request
        [vlTOPp->__Vtableidx7];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx7];
    vlTOPp->__Vtableidx8 = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index 
        = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index
        [vlTOPp->__Vtableidx8];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request 
        = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request
        [vlTOPp->__Vtableidx8];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx8];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x10U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x10U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x10U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x10U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible 
        = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible 
        = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible 
        = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible 
        = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x11U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x11U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x11U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x11U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0U] 
        = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0U] 
        = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0U] 
        = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0U] 
        = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0U] 
        = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                          << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                                      >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0U] 
        = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                          << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                                      >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0U] 
        = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                          << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                                      >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0U] 
        = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                          << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                                      >> 0x14U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) 
           | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) 
           | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                    << 1U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) 
           | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                    << 2U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) 
           | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                    << 3U)));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill 
        = (0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
            << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                      >> 0x17U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] 
        = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                             << 0x39U) 
                                            | (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                << 0x19U) 
                                               | ((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                  >> 7U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] 
        = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                      << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) 
                                            & (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                                << 0x39U) 
                                               | (((QData)((IData)(
                                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                   << 0x19U) 
                                                  | ((QData)((IData)(
                                                                     vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                     >> 7U)))) 
                                           >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
            << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                      >> 0x17U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] 
        = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                             << 0x39U) 
                                            | (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                << 0x19U) 
                                               | ((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                  >> 7U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] 
        = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                      << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) 
                                            & (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                                << 0x39U) 
                                               | (((QData)((IData)(
                                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                   << 0x19U) 
                                                  | ((QData)((IData)(
                                                                     vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                     >> 7U)))) 
                                           >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
            << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                      >> 0x17U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] 
        = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                             << 0x39U) 
                                            | (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                << 0x19U) 
                                               | ((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                  >> 7U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] 
        = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                      << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) 
                                            & (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                                << 0x39U) 
                                               | (((QData)((IData)(
                                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                   << 0x19U) 
                                                  | ((QData)((IData)(
                                                                     vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                     >> 7U)))) 
                                           >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
            << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                      >> 0x17U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] 
        = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                             << 0x39U) 
                                            | (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                << 0x19U) 
                                               | ((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                  >> 7U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] 
        = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                      << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) 
                                            & (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                                << 0x39U) 
                                               | (((QData)((IData)(
                                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                   << 0x19U) 
                                                  | ((QData)((IData)(
                                                                     vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                     >> 7U)))) 
                                           >> 0x20U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] 
        = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) 
           | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                             << 9U) | (0x1fcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x17U)))));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] 
        = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) 
           | (0xf0000000U & (0x10000000U | (0xc0000000U 
                                            & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                               << 5U)))));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] 
        = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) 
           | (0xffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                          << 5U)) | 
                           (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                     >> 0x1bU)))));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] 
        = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) 
           | (0xff000000U & (0x2000000U | (0xfc000000U 
                                           & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                              << 1U)))));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] 
        = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) 
           | (0xfffffU & ((0xfffffeU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                        << 1U)) | (1U 
                                                   & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                      >> 0x1fU)))));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] 
        = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) 
           | (0xfff00000U & (0x300000U | (0xffc00000U 
                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                              << 0x1dU) 
                                             | (0x1fc00000U 
                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                   >> 3U)))))));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] 
        = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                      >> 3U));
    vlTOPp->__Vtableidx3 = vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use;
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index 
        = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index
        [vlTOPp->__Vtableidx3];
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid 
        = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid
        [vlTOPp->__Vtableidx3];
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx3];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                    >> 2U))) & (~ (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x14U))) 
                 & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                       >> 0x17U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                    >> 2U))) & (~ (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x14U))) 
                 & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                       >> 0x17U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                    >> 2U))) & (~ (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x14U))) 
                 & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                       >> 0x17U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                    >> 2U))) & (~ (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x14U))) 
                 & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                       >> 0x17U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                 >> 0x18U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                 >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                            >> 1U)) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x15U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                 >> 0x18U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                 >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                            >> 1U)) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x15U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                 >> 0x18U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                 >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                            >> 1U)) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x15U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                 >> 0x18U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                 >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                            >> 1U)) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x15U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                   >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                  >> 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                   >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                  >> 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                   >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                  >> 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                   >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                  >> 2U)));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r));
    vlTOPp->dram_rsp_ready = (0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready));
    vlTOPp->snp_req_ready = (1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) 
                                   >> (3U & vlTOPp->snp_req_addr)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty 
        = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                            >> 0x16U))))) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty 
        = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                            >> 0x16U))))) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty 
        = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                            >> 0x16U))))) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty 
        = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                            >> 0x16U))))) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->core_req_ready = (0xfU == ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready) 
                                       | (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U];
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = 
        ((0xfcU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) 
         | (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
                  >> 0xaU)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U] 
        = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] 
        = ((0xfffffc00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) 
           | (IData)(((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                                 vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                                 << 0x20U) 
                                                | (QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) 
                      >> 0x20U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U];
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = 
        ((0xf3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) 
         | (0xcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
                    >> 8U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] 
        = ((0x3ffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) 
           | (0xfffffc00U & ((IData)((VL_ULL(0x3ffffffffff) 
                                      & (((QData)((IData)(
                                                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                          << 0x20U) 
                                         | (QData)((IData)(
                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
        = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) 
           | ((0x3ffU & ((IData)((VL_ULL(0x3ffffffffff) 
                                  & (((QData)((IData)(
                                                      vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                      << 0x20U) | (QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                         >> 0x16U)) | (0xfffffc00U 
                                       & ((IData)((
                                                   (VL_ULL(0x3ffffffffff) 
                                                    & (((QData)((IData)(
                                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                                        << 0x20U) 
                                                       | (QData)((IData)(
                                                                         vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) 
                                                   >> 0x20U)) 
                                          << 0xaU))));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U];
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = 
        ((0xcfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) 
         | (0x30U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
                     >> 6U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
        = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) 
           | (0xfff00000U & ((IData)((VL_ULL(0x3ffffffffff) 
                                      & (((QData)((IData)(
                                                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                          << 0x20U) 
                                         | (QData)((IData)(
                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                             << 0x14U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
        = ((0xc0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) 
           | ((0xfffffU & ((IData)((VL_ULL(0x3ffffffffff) 
                                    & (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                        << 0x20U) | (QData)((IData)(
                                                                    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                           >> 0xcU)) | (0xfff00000U 
                                        & ((IData)(
                                                   ((VL_ULL(0x3ffffffffff) 
                                                     & (((QData)((IData)(
                                                                         vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                                         << 0x20U) 
                                                        | (QData)((IData)(
                                                                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) 
                                                    >> 0x20U)) 
                                           << 0x14U))));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U];
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = 
        ((0x3fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) 
         | (0xc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
                     >> 4U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
        = ((0x3fffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) 
           | (0xc0000000U & ((IData)((VL_ULL(0x3ffffffffff) 
                                      & (((QData)((IData)(
                                                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                          << 0x20U) 
                                         | (QData)((IData)(
                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                             << 0x1eU)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] 
        = ((0x3fffffffU & ((IData)((VL_ULL(0x3ffffffffff) 
                                    & (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                        << 0x20U) | (QData)((IData)(
                                                                    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                           >> 2U)) | (0xc0000000U & 
                                      ((IData)(((VL_ULL(0x3ffffffffff) 
                                                 & (((QData)((IData)(
                                                                     vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                                     << 0x20U) 
                                                    | (QData)((IData)(
                                                                      vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) 
                                                >> 0x20U)) 
                                       << 0x1eU)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] 
        = (0x3fffffffU & ((IData)(((VL_ULL(0x3ffffffffff) 
                                    & (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                        << 0x20U) | (QData)((IData)(
                                                                    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) 
                                   >> 0x20U)) >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 
        = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
            ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
                                ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                        ((IData)(1U) 
                                         + (3U & (((IData)(0x1eU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                                  >> 5U)))] 
                                        << ((IData)(0x20U) 
                                            - (0x1fU 
                                               & ((IData)(0x1eU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) 
                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                 (3U & (((IData)(0x1eU) 
                                         * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                        >> 5U))] >> 
                                 (0x1fU & ((IData)(0x1eU) 
                                           * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 
        = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
            ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
                                ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                        ((IData)(1U) 
                                         + (3U & (((IData)(0x1eU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                                  >> 5U)))] 
                                        << ((IData)(0x20U) 
                                            - (0x1fU 
                                               & ((IData)(0x1eU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) 
                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                 (3U & (((IData)(0x1eU) 
                                         * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                        >> 5U))] >> 
                                 (0x1fU & ((IData)(0x1eU) 
                                           * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 
        = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
            ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
                                ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                        ((IData)(1U) 
                                         + (3U & (((IData)(0x1eU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                                  >> 5U)))] 
                                        << ((IData)(0x20U) 
                                            - (0x1fU 
                                               & ((IData)(0x1eU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) 
                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                 (3U & (((IData)(0x1eU) 
                                         * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                        >> 5U))] >> 
                                 (0x1fU & ((IData)(0x1eU) 
                                           * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 
        = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
            ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
                                ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                        ((IData)(1U) 
                                         + (3U & (((IData)(0x1eU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                                  >> 5U)))] 
                                        << ((IData)(0x20U) 
                                            - (0x1fU 
                                               & ((IData)(0x1eU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) 
                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                 (3U & (((IData)(0x1eU) 
                                         * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                        >> 5U))] >> 
                                 (0x1fU & ((IData)(0x1eU) 
                                           * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
            : 0U);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U] 
        = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[1U] 
        = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[2U] 
        = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U] 
        = (0xffffU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))
                       ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U]
                       : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid 
        = (0xfU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))
                    ? ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid) 
                       & VL_NEGATE_I((IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)))))
                    : ((vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] 
                        >> 0x10U) & VL_NEGATE_I((IData)(
                                                        (1U 
                                                         & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) 
                 & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) 
                 & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) 
                 & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) 
                 & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 0U;
    if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
        [0U]) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 1U;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 0U;
    if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
        [0U]) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 1U;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 0U;
    if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
        [0U]) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 1U;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 0U;
    if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
        [0U]) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 1U;
    }
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] 
        = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) 
           | (0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U]));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen 
        = ((VL_ULL(0xffffffffffff0000) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) 
           | (IData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                          << 0xaU) 
                                         | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                            >> 0x16U))))));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[1U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[2U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[3U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] 
        = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) 
           | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                             << 6U) | (0x3cU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
                                                >> 0x1aU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] 
        = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) 
           | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                             << 0x1cU)));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] 
        = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) 
           | (0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                           >> 4U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen 
        = ((VL_ULL(0xffffffff0000ffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) 
           | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                           << 0xaU) 
                                          | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                             >> 0x16U))))) 
              << 0x10U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[4U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[5U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[6U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[7U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] 
        = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) 
           | (0xf0000000U & (0x10000000U | (0xc0000000U 
                                            & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
                                               << 2U)))));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] 
        = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) 
           | (0xffffffU & ((0xffffffcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                          << 2U)) | 
                           (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
                                  >> 0x1eU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] 
        = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) 
           | (0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                             << 0x18U)));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] 
        = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) 
           | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                          >> 8U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen 
        = ((VL_ULL(0xffff0000ffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) 
           | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                           << 0xaU) 
                                          | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                             >> 0x16U))))) 
              << 0x20U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[8U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[9U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xaU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xbU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] 
        = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) 
           | (0xff000000U & (0x2000000U | (0xfc000000U 
                                           & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                               << 0x1eU) 
                                              | (0x3c000000U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
                                                    >> 2U)))))));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] 
        = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) 
           | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                          >> 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] 
        = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) 
           | (0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                             << 0x14U)));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] 
        = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                      >> 0xcU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen 
        = ((VL_ULL(0xffffffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) 
           | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                           << 0xaU) 
                                          | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                             >> 0x16U))))) 
              << 0x30U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xcU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xdU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xeU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xfU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] 
        = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) 
           | (0xfff00000U & (0x300000U | (0xffc00000U 
                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                              << 0x1aU) 
                                             | (0x3c00000U 
                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
                                                   >> 6U)))))));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] 
        = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                      >> 6U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
               ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) 
                        == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                        [0U])) : 0U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         << 6U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] 
                                                   >> 0x1aU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                         << 0xcU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         >> 0x14U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                         << 0x12U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                           >> 0xeU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                         << 0x18U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                           >> 8U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 0x1eU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                           >> 2U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 4U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                                   >> 0x1cU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 6U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                         << 0xaU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         >> 0x16U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 7U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                         << 0x10U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                           >> 0x10U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                         << 0x16U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                           >> 0xaU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 9U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 0x1cU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                           >> 4U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xaU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 2U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                                   >> 0x1eU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xbU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         << 8U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                                   >> 0x18U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                         << 0xeU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         >> 0x12U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xdU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                         << 0x14U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                           >> 0xcU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                        >> 6U)) == 
                         vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
          [0U])][0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
          [0U])][1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
          [0U])][2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
          [0U])][3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
        = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                             [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag
           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
             [0U])]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
        = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
                              >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                                  [0U]))) << 5U)) | 
           ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty 
                               >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                                   [0U]))) << 4U)) 
            | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                             [0U])] >> 0xcU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
               ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) 
                        == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                        [0U])) : 0U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         << 6U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] 
                                                   >> 0x1aU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                         << 0xcU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         >> 0x14U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                         << 0x12U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                           >> 0xeU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                         << 0x18U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                           >> 8U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 0x1eU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                           >> 2U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 4U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                                   >> 0x1cU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 6U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                         << 0xaU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         >> 0x16U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 7U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                         << 0x10U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                           >> 0x10U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                         << 0x16U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                           >> 0xaU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 9U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 0x1cU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                           >> 4U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xaU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 2U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                                   >> 0x1eU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xbU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         << 8U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                                   >> 0x18U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                         << 0xeU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         >> 0x12U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xdU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                         << 0x14U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                           >> 0xcU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                        >> 6U)) == 
                         vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
          [0U])][0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
          [0U])][1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
          [0U])][2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
          [0U])][3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
        = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                             [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag
           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
             [0U])]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
        = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
                              >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                                  [0U]))) << 5U)) | 
           ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty 
                               >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                                   [0U]))) << 4U)) 
            | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                             [0U])] >> 0xcU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
               ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) 
                        == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                        [0U])) : 0U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         << 6U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] 
                                                   >> 0x1aU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                         << 0xcU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         >> 0x14U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                         << 0x12U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                           >> 0xeU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                         << 0x18U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                           >> 8U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 0x1eU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                           >> 2U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 4U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                                   >> 0x1cU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 6U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                         << 0xaU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         >> 0x16U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 7U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                         << 0x10U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                           >> 0x10U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                         << 0x16U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                           >> 0xaU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 9U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 0x1cU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                           >> 4U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xaU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 2U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                                   >> 0x1eU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xbU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         << 8U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                                   >> 0x18U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                         << 0xeU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         >> 0x12U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xdU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                         << 0x14U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                           >> 0xcU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                        >> 6U)) == 
                         vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
          [0U])][0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
          [0U])][1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
          [0U])][2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
          [0U])][3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
        = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                             [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag
           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
             [0U])]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
        = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
                              >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                                  [0U]))) << 5U)) | 
           ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty 
                               >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                                   [0U]))) << 4U)) 
            | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                             [0U])] >> 0xcU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
               ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) 
                        == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                        [0U])) : 0U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         << 6U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] 
                                                   >> 0x1aU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                         << 0xcU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         >> 0x14U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                         << 0x12U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                           >> 0xeU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                         << 0x18U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                           >> 8U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 0x1eU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                           >> 2U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 4U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                                   >> 0x1cU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 6U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                         << 0xaU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         >> 0x16U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 7U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                         << 0x10U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                           >> 0x10U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                         << 0x16U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                           >> 0xaU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 9U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 0x1cU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                           >> 4U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xaU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 2U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                                   >> 0x1eU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xbU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         << 8U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                                   >> 0x18U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                         << 0xeU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         >> 0x12U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xdU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                         << 0x14U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                           >> 0xcU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                        >> 6U)) == 
                         vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
          [0U])][0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
          [0U])][1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
          [0U])][2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
          [0U])][3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
        = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                             [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag
           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
             [0U])]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
        = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
                              >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                                  [0U]))) << 5U)) | 
           ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty 
                               >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                                   [0U]))) << 4U)) 
            | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                             [0U])] >> 0xcU))));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           << 5U)) | (0xfffffffU & 
                                      ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                        << 0x19U) | 
                                       (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                        >> 7U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                           << 3U)) | (0xfffffffU & 
                                      ((0xfffffe0U 
                                        & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                                           << 5U)) 
                                       | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                          >> 0x1bU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] 
        = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                           << 5U)) | (0xfffffffU & 
                                      ((0x3ffffcU & 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                         >> 1U)) | 
                                       (3U & ((0xffffff8U 
                                               & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  << 3U)) 
                                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x1dU))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] 
        = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
                           << 7U)) | ((0xffffffc0U 
                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in) 
                                          << 6U)) | 
                                      (0x3fU & ((0x3fffe0U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                    << 5U)) 
                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                                   >> 0x1bU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           << 5U)) | (0xfffffffU & 
                                      ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                        << 0x19U) | 
                                       (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                        >> 7U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                           << 3U)) | (0xfffffffU & 
                                      ((0xfffffe0U 
                                        & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                                           << 5U)) 
                                       | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                          >> 0x1bU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] 
        = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                           << 5U)) | (0xfffffffU & 
                                      ((0x3ffffcU & 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                         >> 1U)) | 
                                       (3U & ((0xffffff8U 
                                               & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  << 3U)) 
                                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x1dU))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] 
        = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
                           << 7U)) | ((0xffffffc0U 
                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in) 
                                          << 6U)) | 
                                      (0x3fU & ((0x3fffe0U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                    << 5U)) 
                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                                   >> 0x1bU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           << 5U)) | (0xfffffffU & 
                                      ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                        << 0x19U) | 
                                       (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                        >> 7U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                           << 3U)) | (0xfffffffU & 
                                      ((0xfffffe0U 
                                        & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                                           << 5U)) 
                                       | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                          >> 0x1bU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] 
        = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                           << 5U)) | (0xfffffffU & 
                                      ((0x3ffffcU & 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                         >> 1U)) | 
                                       (3U & ((0xffffff8U 
                                               & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  << 3U)) 
                                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x1dU))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] 
        = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
                           << 7U)) | ((0xffffffc0U 
                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in) 
                                          << 6U)) | 
                                      (0x3fU & ((0x3fffe0U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                    << 5U)) 
                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                                   >> 0x1bU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           << 5U)) | (0xfffffffU & 
                                      ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                        << 0x19U) | 
                                       (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                        >> 7U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                           << 3U)) | (0xfffffffU & 
                                      ((0xfffffe0U 
                                        & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                                           << 5U)) 
                                       | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                          >> 0x1bU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] 
        = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                           << 5U)) | (0xfffffffU & 
                                      ((0x3ffffcU & 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                         >> 1U)) | 
                                       (3U & ((0xffffff8U 
                                               & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  << 3U)) 
                                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x1dU))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] 
        = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
                           << 7U)) | ((0xffffffc0U 
                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in) 
                                          << 6U)) | 
                                      (0x3fU & ((0x3fffe0U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                    << 5U)) 
                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                                   >> 0x1bU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x18U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x18U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x18U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x18U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) 
                 & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) 
                 & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) 
                 & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) 
                 & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid 
        = (0xfU & ((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) 
                   & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid 
        = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) 
                    >> 4U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid 
        = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) 
                    >> 8U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid 
        = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) 
                    >> 0xcU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready)))));
    vlTOPp->core_rsp_tag = ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                             ? (VL_ULL(0x3ffffffffff) 
                                & (((0U == (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                     ? VL_ULL(0) : 
                                    ((QData)((IData)(
                                                     vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                     ((IData)(2U) 
                                                      + 
                                                      (7U 
                                                       & (((IData)(0x2aU) 
                                                           * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                          >> 5U)))])) 
                                     << ((IData)(0x40U) 
                                         - (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                   | (((QData)((IData)(
                                                       vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                       ((IData)(1U) 
                                                        + 
                                                        (7U 
                                                         & (((IData)(0x2aU) 
                                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                            >> 5U)))])) 
                                       << ((0U == (0x1fU 
                                                   & ((IData)(0x2aU) 
                                                      * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                            ? 0x20U
                                            : ((IData)(0x20U) 
                                               - (0x1fU 
                                                  & ((IData)(0x2aU) 
                                                     * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                      | ((QData)((IData)(
                                                         vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                         (7U 
                                                          & (((IData)(0x2aU) 
                                                              * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                             >> 5U))])) 
                                         >> (0x1fU 
                                             & ((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))))
                             : VL_ULL(0));
    vlTOPp->core_rsp_valid = 0U;
    if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
         & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) 
            == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                    * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                 ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) 
                                               * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                               ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                       ((IData)(1U) 
                                        + (7U & (((IData)(0x2aU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                 >> 5U)))] 
                                       << ((IData)(0x20U) 
                                           - (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                             | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                (7U & (((IData)(0x2aU) 
                                        * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                       >> 5U))] >> 
                                (0x1fU & ((IData)(0x2aU) 
                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                 : 0U)))) {
        vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) 
                                  | ((IData)(1U) << 
                                     (3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid))));
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                               << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] 
                                            >> 0xaU))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) 
                                  | ((IData)(1U) << 
                                     (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                            >> 2U))));
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                               << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                                           >> 0x14U))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) 
                                  | ((IData)(1U) << 
                                     (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                            >> 4U))));
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] 
                               << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                                         >> 0x1eU))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) 
                                  | ((IData)(1U) << 
                                     (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                            >> 6U))));
    }
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U] = 0U;
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U;
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U;
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U] = 0U;
    if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
         & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) 
            == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                    * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                 ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) 
                                               * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                               ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                       ((IData)(1U) 
                                        + (7U & (((IData)(0x2aU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                 >> 5U)))] 
                                       << ((IData)(0x20U) 
                                           - (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                             | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                (7U & (((IData)(0x2aU) 
                                        * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                       >> 5U))] >> 
                                (0x1fU & ((IData)(0x2aU) 
                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                 : 0U)))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                       << 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, 
                          vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U]);
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                               << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] 
                                            >> 0xaU))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                       << 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, 
                          vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U]);
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                               << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                                           >> 0x14U))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                       << 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, 
                          vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U]);
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] 
                               << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                                         >> 0x1eU))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                       >> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, 
                          vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]);
    }
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) 
           | ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
              & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) 
                 == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                      ? (0xffU & (((0U == (0x1fU & 
                                           ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                    ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                            ((IData)(1U) 
                                             + (7U 
                                                & (((IData)(0x2aU) 
                                                    * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                   >> 5U)))] 
                                            << ((IData)(0x20U) 
                                                - (0x1fU 
                                                   & ((IData)(0x2aU) 
                                                      * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                  | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                     (7U & (((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                            >> 5U))] 
                                     >> (0x1fU & ((IData)(0x2aU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                      : 0U))));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) 
           | (0xfffffffeU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
                             & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                                            << 0x16U) 
                                           | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] 
                                              >> 0xaU))) 
                                 == ((0xa7U >= (0xffU 
                                                & ((IData)(0x2aU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                      ? (0xffU & ((
                                                   (0U 
                                                    == 
                                                    (0x1fU 
                                                     & ((IData)(0x2aU) 
                                                        * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                                    ? 0U
                                                    : 
                                                   (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                    ((IData)(1U) 
                                                     + 
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U)))] 
                                                    << 
                                                    ((IData)(0x20U) 
                                                     - 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                                  | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U))] 
                                                     >> 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                                      : 0U)) << 1U))));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) 
           | (0xfffffffcU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
                             & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                                            << 0xcU) 
                                           | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                                              >> 0x14U))) 
                                 == ((0xa7U >= (0xffU 
                                                & ((IData)(0x2aU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                      ? (0xffU & ((
                                                   (0U 
                                                    == 
                                                    (0x1fU 
                                                     & ((IData)(0x2aU) 
                                                        * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                                    ? 0U
                                                    : 
                                                   (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                    ((IData)(1U) 
                                                     + 
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U)))] 
                                                    << 
                                                    ((IData)(0x20U) 
                                                     - 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                                  | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U))] 
                                                     >> 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                                      : 0U)) << 2U))));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) 
           | (0xfffffff8U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
                             & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] 
                                            << 2U) 
                                           | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                                              >> 0x1eU))) 
                                 == ((0xa7U >= (0xffU 
                                                & ((IData)(0x2aU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                      ? (0xffU & ((
                                                   (0U 
                                                    == 
                                                    (0x1fU 
                                                     & ((IData)(0x2aU) 
                                                        * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                                    ? 0U
                                                    : 
                                                   (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                    ((IData)(1U) 
                                                     + 
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U)))] 
                                                    << 
                                                    ((IData)(0x20U) 
                                                     - 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                                  | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U))] 
                                                     >> 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                                      : 0U)) << 3U))));
    vlTOPp->__Vtableidx1 = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index 
        = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index
        [vlTOPp->__Vtableidx1];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request 
        = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request
        [vlTOPp->__Vtableidx1];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx1];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
              & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
             & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
              & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
             & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
              & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
             & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
              & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
             & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe)));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = 
        ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) 
         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = 
        ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) 
         | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) 
            << 1U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) 
              << 1U));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = 
        ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) 
         | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) 
            << 2U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) 
              << 2U));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = 
        ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) 
         | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) 
            << 3U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) 
              << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
              [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] 
        = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                       << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
                                   >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] 
        = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
              [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] 
        = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                       << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
                                   >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] 
        = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
              [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] 
        = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                       << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
                                   >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] 
        = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
              [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] 
        = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                       << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
                                   >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] 
        = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]);
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value 
        = (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) 
           | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) 
               ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
                                 & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) 
                                & ((0x3ffffffU & ((
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   << 7U) 
                                                  | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                     >> 0x19U))) 
                                   == (0x3ffffffU & 
                                       vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) 
                 | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
                     & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                     [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                              << 7U) 
                                             | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                >> 0x19U))) 
                              == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                              [0U]))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
           & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
           & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
              >> 0x1aU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
                                 & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) 
                                & ((0x3ffffffU & ((
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   << 7U) 
                                                  | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                     >> 0x19U))) 
                                   == (0x3ffffffU & 
                                       vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) 
                 | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
                     & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                     [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                              << 7U) 
                                             | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                >> 0x19U))) 
                              == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                              [0U]))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
           & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
           & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
              >> 0x1aU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
                                 & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) 
                                & ((0x3ffffffU & ((
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   << 7U) 
                                                  | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                     >> 0x19U))) 
                                   == (0x3ffffffU & 
                                       vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) 
                 | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
                     & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                     [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                              << 7U) 
                                             | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                >> 0x19U))) 
                              == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                              [0U]))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
           & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
           & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
              >> 0x1aU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
                                 & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) 
                                & ((0x3ffffffU & ((
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   << 7U) 
                                                  | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                     >> 0x19U))) 
                                   == (0x3ffffffU & 
                                       vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) 
                 | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
                     & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                     [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                              << 7U) 
                                             | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                >> 0x19U))) 
                              == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                              [0U]))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
           & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
           & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
              >> 0x1aU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing 
        = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] 
        = (IData)(vlTOPp->core_req_tag);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] 
        = ((0xfffffc00U & (vlTOPp->core_req_data[0U] 
                           << 0xaU)) | (IData)((vlTOPp->core_req_tag 
                                                >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] 
        = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] 
        = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] 
        = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] 
        = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] 
                           << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] 
                                                  >> 0x16U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] 
        = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid) 
                           << 0x16U)) | ((0xfffc0000U 
                                          & ((IData)(vlTOPp->core_req_rw) 
                                             << 0x12U)) 
                                         | ((0xfffffffcU 
                                             & ((IData)(vlTOPp->core_req_byteen) 
                                                << 2U)) 
                                            | (0x3ffU 
                                               & (vlTOPp->core_req_addr[3U] 
                                                  >> 0x16U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing 
        = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] 
        = (IData)(vlTOPp->core_req_tag);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] 
        = ((0xfffffc00U & (vlTOPp->core_req_data[0U] 
                           << 0xaU)) | (IData)((vlTOPp->core_req_tag 
                                                >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] 
        = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] 
        = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] 
        = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] 
        = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] 
                           << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] 
                                                  >> 0x16U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] 
        = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid) 
                           << 0x16U)) | ((0xfffc0000U 
                                          & ((IData)(vlTOPp->core_req_rw) 
                                             << 0x12U)) 
                                         | ((0xfffffffcU 
                                             & ((IData)(vlTOPp->core_req_byteen) 
                                                << 2U)) 
                                            | (0x3ffU 
                                               & (vlTOPp->core_req_addr[3U] 
                                                  >> 0x16U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing 
        = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] 
        = (IData)(vlTOPp->core_req_tag);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] 
        = ((0xfffffc00U & (vlTOPp->core_req_data[0U] 
                           << 0xaU)) | (IData)((vlTOPp->core_req_tag 
                                                >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] 
        = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] 
        = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] 
        = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] 
        = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] 
                           << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] 
                                                  >> 0x16U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] 
        = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid) 
                           << 0x16U)) | ((0xfffc0000U 
                                          & ((IData)(vlTOPp->core_req_rw) 
                                             << 0x12U)) 
                                         | ((0xfffffffcU 
                                             & ((IData)(vlTOPp->core_req_byteen) 
                                                << 2U)) 
                                            | (0x3ffU 
                                               & (vlTOPp->core_req_addr[3U] 
                                                  >> 0x16U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing 
        = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] 
        = (IData)(vlTOPp->core_req_tag);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] 
        = ((0xfffffc00U & (vlTOPp->core_req_data[0U] 
                           << 0xaU)) | (IData)((vlTOPp->core_req_tag 
                                                >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] 
        = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] 
        = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] 
        = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] 
        = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] 
                           << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] 
                                                  >> 0x16U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] 
        = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid) 
                           << 0x16U)) | ((0xfffc0000U 
                                          & ((IData)(vlTOPp->core_req_rw) 
                                             << 0x12U)) 
                                         | ((0xfffffffcU 
                                             & ((IData)(vlTOPp->core_req_byteen) 
                                                << 2U)) 
                                            | (0x3ffU 
                                               & (vlTOPp->core_req_addr[3U] 
                                                  >> 0x16U)))));
    vlTOPp->core_rsp_data[0U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U];
    vlTOPp->core_rsp_data[1U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U];
    vlTOPp->core_rsp_data[2U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U];
    vlTOPp->core_rsp_data[3U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U];
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual) 
           & VL_NEGATE_I((IData)((IData)(vlTOPp->core_rsp_ready))));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) 
                 >> (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)));
    vlTOPp->__Vtableidx4 = vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid;
    vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank 
        = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank
        [vlTOPp->__Vtableidx4];
    vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid 
        = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid
        [vlTOPp->__Vtableidx4];
    vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx4];
    vlTOPp->__Vtableidx2 = vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank 
        = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank
        [vlTOPp->__Vtableidx2];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid 
        = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid
        [vlTOPp->__Vtableidx2];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx2];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
            [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match 
        = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                        [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
            [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match 
        = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                        [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
            [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match 
        = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                        [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
            [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match 
        = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                        [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) 
                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing 
        = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
             & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                   >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) 
                                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) 
                                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
               & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                  | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                      >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                      >> 0x1bU))))) 
              & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) 
                     | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) 
                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) 
             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e 
        = (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
             [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1
                     [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
                               | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) 
                                  & (((0x3ffffffU & 
                                       ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                         << 7U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                   >> 0x19U))) 
                                      == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                                      [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  >> 0x14U)))))) 
           | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1
               [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) 
                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing 
        = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
             & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                   >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) 
                                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) 
                                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) 
           | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
                << 1U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                           << 1U) | (0x7eU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                               >> 0x19U) 
                                              & ((~ 
                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x1bU)) 
                                                 << 1U))))) 
              & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) 
                      | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) 
                     | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall))) 
                 << 1U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) 
             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e 
        = (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
             [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1
                     [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
                               | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) 
                                  & (((0x3ffffffU & 
                                       ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                         << 7U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                   >> 0x19U))) 
                                      == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                                      [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  >> 0x14U)))))) 
           | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1
               [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) 
                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing 
        = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
             & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                   >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) 
                                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) 
                                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) 
           | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
                << 2U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                           << 2U) | (0xfcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                               >> 0x18U) 
                                              & ((~ 
                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x1bU)) 
                                                 << 2U))))) 
              & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) 
                      | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) 
                     | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall))) 
                 << 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) 
             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e 
        = (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
             [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1
                     [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
                               | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) 
                                  & (((0x3ffffffU & 
                                       ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                         << 7U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                   >> 0x19U))) 
                                      == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                                      [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  >> 0x14U)))))) 
           | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1
               [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) 
                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing 
        = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
             & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                   >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) 
                                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) 
                                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) 
           | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
                << 3U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                           << 3U) | (0x1f8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                >> 0x17U) 
                                               & ((~ 
                                                   (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                    >> 0x1bU)) 
                                                  << 3U))))) 
              & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) 
                      | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) 
                     | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall))) 
                 << 3U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) 
             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e 
        = (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
             [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1
                     [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
                               | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) 
                                  & (((0x3ffffffU & 
                                       ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                         << 7U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                   >> 0x19U))) 
                                      == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                                      [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  >> 0x14U)))))) 
           | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1
               [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)) 
                 & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) 
                     >> 1U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) 
                     >> 2U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) 
                     >> 3U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->snp_rsp_valid = vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid;
    vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)));
    vlTOPp->snp_rsp_tag = ((0x6fU >= (0x7fU & ((IData)(0x1cU) 
                                               * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))))
                            ? (0xfffffffU & (((0U == 
                                               (0x1fU 
                                                & ((IData)(0x1cU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))))
                                               ? 0U
                                               : (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[
                                                  ((IData)(1U) 
                                                   + 
                                                   (3U 
                                                    & (((IData)(0x1cU) 
                                                        * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) 
                                                       >> 5U)))] 
                                                  << 
                                                  ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x1cU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) 
                                             | (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[
                                                (3U 
                                                 & (((IData)(0x1cU) 
                                                     * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) 
                                                    >> 5U))] 
                                                >> 
                                                (0x1fU 
                                                 & ((IData)(0x1cU) 
                                                    * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))))))
                            : 0U);
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = 
        ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) 
         | ((IData)(vlTOPp->snp_rsp_ready) & (0U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = 
        ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) 
         | (((IData)(vlTOPp->snp_rsp_ready) & (1U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) 
            << 1U));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = 
        ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) 
         | (((IData)(vlTOPp->snp_rsp_ready) & (2U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) 
            << 2U));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = 
        ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) 
         | (((IData)(vlTOPp->snp_rsp_ready) & (3U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) 
            << 3U));
    vlTOPp->dram_req_rw = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid;
    vlTOPp->dram_req_valid = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) 
                              | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop 
        = (((~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)) 
            & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)) 
           & (IData)(vlTOPp->dram_req_ready));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)));
    vlTOPp->dram_req_byteen = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                ? (0xffffU & (IData)(
                                                     (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen 
                                                      >> 
                                                      (0x3fU 
                                                       & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                          << 4U)))))
                                : 0xffffU);
    vlTOPp->dram_req_data[0U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                  ? (((0U == (0x1fU 
                                              & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                 << 7U)))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                               ((IData)(1U) 
                                                + (0xcU 
                                                   & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                      << 2U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                       << 7U))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                        (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                 << 2U))] 
                                        >> (0x1fU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 7U))))
                                  : 0U);
    vlTOPp->dram_req_data[1U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                  ? (((0U == (0x1fU 
                                              & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                 << 7U)))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                               ((IData)(2U) 
                                                + (0xcU 
                                                   & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                      << 2U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                       << 7U))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                        ((IData)(1U) 
                                         + (0xcU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 2U)))] 
                                        >> (0x1fU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 7U))))
                                  : 0U);
    vlTOPp->dram_req_data[2U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                  ? (((0U == (0x1fU 
                                              & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                 << 7U)))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                               ((IData)(3U) 
                                                + (0xcU 
                                                   & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                      << 2U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                       << 7U))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                        ((IData)(2U) 
                                         + (0xcU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 2U)))] 
                                        >> (0x1fU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 7U))))
                                  : 0U);
    vlTOPp->dram_req_data[3U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                  ? (((0U == (0x1fU 
                                              & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                 << 7U)))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                               ((IData)(4U) 
                                                + (0xcU 
                                                   & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                      << 2U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                       << 7U))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                        ((IData)(3U) 
                                         + (0xcU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 2U)))] 
                                        >> (0x1fU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 7U))))
                                  : 0U);
    vlTOPp->dram_req_addr = (0xfffffffU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                            ? ((0x6fU 
                                                >= 
                                                (0x7fU 
                                                 & ((IData)(0x1cU) 
                                                    * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))))
                                                ? (
                                                   ((0U 
                                                     == 
                                                     (0x1fU 
                                                      & ((IData)(0x1cU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))))
                                                     ? 0U
                                                     : 
                                                    (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[
                                                     ((IData)(1U) 
                                                      + 
                                                      (3U 
                                                       & (((IData)(0x1cU) 
                                                           * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) 
                                                          >> 5U)))] 
                                                     << 
                                                     ((IData)(0x20U) 
                                                      - 
                                                      (0x1fU 
                                                       & ((IData)(0x1cU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))))) 
                                                   | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[
                                                      (3U 
                                                       & (((IData)(0x1cU) 
                                                           * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) 
                                                          >> 5U))] 
                                                      >> 
                                                      (0x1fU 
                                                       & ((IData)(0x1cU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))))
                                                : 0U)
                                            : ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)
                                                ? (
                                                   (0x6fU 
                                                    >= 
                                                    (0x7fU 
                                                     & ((IData)(0x1cU) 
                                                        * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))
                                                    ? 
                                                   (((0U 
                                                      == 
                                                      (0x1fU 
                                                       & ((IData)(0x1cU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))
                                                      ? 0U
                                                      : 
                                                     (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[
                                                      ((IData)(1U) 
                                                       + 
                                                       (3U 
                                                        & (((IData)(0x1cU) 
                                                            * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) 
                                                           >> 5U)))] 
                                                      << 
                                                      ((IData)(0x20U) 
                                                       - 
                                                       (0x1fU 
                                                        & ((IData)(0x1cU) 
                                                           * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) 
                                                    | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[
                                                       (3U 
                                                        & (((IData)(0x1cU) 
                                                            * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) 
                                                           >> 5U))] 
                                                       >> 
                                                       (0x1fU 
                                                        & ((IData)(0x1cU) 
                                                           * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))
                                                    : 0U)
                                                : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr)));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) 
           | ((IData)(vlTOPp->dram_req_ready) & (0U 
                                                 == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) 
           | (((IData)(vlTOPp->dram_req_ready) & (1U 
                                                  == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) 
              << 1U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) 
           | (((IData)(vlTOPp->dram_req_ready) & (2U 
                                                  == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) 
              << 2U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) 
           | (((IData)(vlTOPp->dram_req_ready) & (3U 
                                                  == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) 
              << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
            [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                      [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                               [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss 
        = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
              [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
                      [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                                [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                                          [0U])) | 
           ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
               [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
                       [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                       [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
            [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                      [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                               [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss 
        = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
              [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1
                      [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                                [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                                          [0U])) | 
           ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
               [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1
                       [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                       [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
            [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                      [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                               [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss 
        = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
              [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1
                      [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                                [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                                          [0U])) | 
           ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
               [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1
                       [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                       [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
            [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                      [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                               [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss 
        = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
              [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
                      [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                                [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                                          [0U])) | 
           ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
               [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
                       [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                       [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending 
        = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
               [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) 
            & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
               [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1
            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending 
        = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1
               [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) 
            & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
               [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1
            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending 
        = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1
               [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) 
            & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
               [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U] 
        = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U] 
        = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U] 
        = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U] 
        = ((0xffff0000U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid) 
                           << 0x10U)) | vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing 
        = (((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending 
        = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
               [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) 
            & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
               [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid) 
           & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) 
              >> 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) 
              >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) 
              >> 3U));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing 
        = ((((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading 
        = ((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) 
             & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) 
            & (~ ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] 
                                             >> 0x10U))))) 
                  | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->dram_req_tag = vlTOPp->dram_req_addr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid) 
           & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) 
              >> 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) 
              >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) 
              >> 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1
           [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1
           [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1
           [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1
           [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1
           [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1
           [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1
           [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1
           [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1
           [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1
           [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1
           [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1
           [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1
           [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1
           [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1
           [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1
           [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head 
        = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible));
    __Vtemp146[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                ? (
                                                   (VL_ULL(0x1ffffffffff80) 
                                                    & (((QData)((IData)(
                                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                        [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                        << 0x3eU) 
                                                       | (((QData)((IData)(
                                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                           [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                           << 0x1eU) 
                                                          | (VL_ULL(0x3fffffffffffff80) 
                                                             & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                >> 2U))))) 
                                                   | (QData)((IData)(
                                                                     (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                       << 6U) 
                                                                      | ((0x3cU 
                                                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                              << 0x1eU) 
                                                                             | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                         | (3U 
                                                                            & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                               | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                    ? 
                                                   ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                     << 7U) 
                                                    | (QData)((IData)(
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                        << 6U) 
                                                                       | ((0x3cU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                               >> 
                                                                               (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                              << 2U)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                    : 
                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                     ? 
                                                    ((QData)((IData)(
                                                                     (0xfffffffU 
                                                                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                     << 7U)
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                                      << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual));
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                                       ? ((VL_ULL(0x1ffffffffff80) 
                                           & (((QData)((IData)(
                                                               vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                               [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                               << 0x3eU) 
                                              | (((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                  [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                  << 0x1eU) 
                                                 | (VL_ULL(0x3fffffffffffff80) 
                                                    & ((QData)((IData)(
                                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                       >> 2U))))) 
                                          | (QData)((IData)(
                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) 
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                                                             | ((0x3cU 
                                                                 & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                     [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                     << 0x1eU) 
                                                                    | (0x3ffffffcU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 2U)))) 
                                                                | (3U 
                                                                   & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                       << 0xdU) 
                                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                         [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                         >> 0x13U))))))))
                                       : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                           ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
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                                              | (QData)((IData)(
                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                  << 6U) 
                                                                 | ((0x3cU 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                         >> 
                                                                         (0xfU 
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                                                                             << 2U))) 
                                                                        << 2U)) 
                                                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                           : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                               ? ((QData)((IData)(
                                                                  (0xfffffffU 
                                                                   & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                  << 7U)
                                               : VL_ULL(0))))) 
                             >> 0x1fU)) | (0xfffffffeU 
                                           & ((IData)(
                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                         ? 
                                                        ((VL_ULL(0x1ffffffffff80) 
                                                          & (((QData)((IData)(
                                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                              << 0x3eU) 
                                                             | (((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                                 << 0x1eU) 
                                                                | (VL_ULL(0x3fffffffffffff80) 
                                                                   & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                      >> 2U))))) 
                                                         | (QData)((IData)(
                                                                           (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                             << 6U) 
                                                                            | ((0x3cU 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                               | (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                         : 
                                                        ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                          ? 
                                                         ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                           << 7U) 
                                                          | (QData)((IData)(
                                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                              << 6U) 
                                                                             | ((0x3cU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                                >> 
                                                                                (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                                << 2U)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                          : 
                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                           ? 
                                                          ((QData)((IData)(
                                                                           (0xfffffffU 
                                                                            & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                           << 7U)
                                                           : VL_ULL(0)))) 
                                                       >> 0x20U)) 
                                              << 1U)));
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                                                                ((0x80000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 1U))
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 1U
                                                                        : 0U)) 
                                                                     << 0x1fU)) 
                                                                 | ((0x40000000U 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                          ? 
                                                                         (1U 
                                                                          & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                          : 
                                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                           ? 
                                                                          (1U 
                                                                           & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                           : 0U)) 
                                                                        << 0x1eU)) 
                                                                    | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                          ? 1U
                                                                          : 
                                                                         (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                           ? 1U
                                                                           : 
                                                                          (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                            & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                            ? 1U
                                                                            : 0U))) 
                                                                        << 0x1dU) 
                                                                       | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) 
                                                                              | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) 
                                                                            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) 
                                                                           << 0x1cU) 
                                                                          | ((0xffffffcU 
                                                                              & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                             | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                << 0x20U) 
                                               | (QData)((IData)(
                                                                 ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                   ? 
                                                                  ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                    [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                    << 0xbU) 
                                                                   | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                      [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                      >> 0x15U))
                                                                   : 
                                                                  ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                    ? 
                                                                   (((0U 
                                                                      == 
                                                                      (0x1fU 
                                                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                          << 5U)))
                                                                      ? 0U
                                                                      : 
                                                                     (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                      ((IData)(1U) 
                                                                       + 
                                                                       (3U 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                      << 
                                                                      ((IData)(0x20U) 
                                                                       - 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                           << 5U))))) 
                                                                    | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                       (3U 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                       >> 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                           << 5U))))
                                                                    : 0U)))))) 
                                      << 0x12U)) | 
                      __Vtemp146[5U]);
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                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
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                                                              | ((0x40000000U 
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                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
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                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) 
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                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) 
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                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
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                                                                                (0x3ffffffU 
                                                                                & (((0U 
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                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
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                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
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                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
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                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                                (0x3ffffffU 
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                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
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                                                                                >> 0x1dU)))
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                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                                (3U 
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                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
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                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
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                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
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                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
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                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
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                                                                    + 
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                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
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                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
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                                                                    >> 
                                                                    (0x1fU 
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                                                                        << 5U))))
                                                                 : 0U)))))) 
                                   >> 0xeU)) | (0xfffc0000U 
                                                & ((IData)(
                                                           ((((QData)((IData)(
                                                                              ((0x80000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                                >> 1U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 0U)) 
                                                                                << 0x1fU)) 
                                                                               | ((0x40000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (1U 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                                 : 0U)) 
                                                                                << 0x1eU)) 
                                                                                | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                                 ? 1U
                                                                                 : 0U))) 
                                                                                << 0x1dU) 
                                                                                | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) 
                                                                                << 0x1cU) 
                                                                                | ((0xffffffcU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                                | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                              << 0x20U) 
                                                             | (QData)((IData)(
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xbU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x15U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U)))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))
                                                                                 : 0U))))) 
                                                            >> 0x20U)) 
                                                   << 0x12U)));
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                                                             ((0x80000000U 
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                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
                                                                        & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U))))) 
                                           >> 0x20U)) 
                                  >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]
            : 0x39U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] 
        = __Vtemp146[4U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] 
        = __Vtemp147[5U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] 
        = __Vtemp147[6U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] 
        = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                           << 0x12U)) | __Vtemp147[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) 
           | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) 
                 & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
                    [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
               [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head 
        = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible));
    __Vtemp160[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                ? (
                                                   (VL_ULL(0x1ffffffffff80) 
                                                    & (((QData)((IData)(
                                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                        [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                        << 0x3eU) 
                                                       | (((QData)((IData)(
                                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                           [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                           << 0x1eU) 
                                                          | (VL_ULL(0x3fffffffffffff80) 
                                                             & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                >> 2U))))) 
                                                   | (QData)((IData)(
                                                                     (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                       << 6U) 
                                                                      | ((0x3cU 
                                                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                              << 0x1eU) 
                                                                             | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                         | (3U 
                                                                            & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                               | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                    ? 
                                                   ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                     << 7U) 
                                                    | (QData)((IData)(
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                        << 6U) 
                                                                       | ((0x3cU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                               >> 
                                                                               (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                              << 2U)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                    : 
                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                     ? 
                                                    ((QData)((IData)(
                                                                     (0xfffffffU 
                                                                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                     << 7U)
                                                     : VL_ULL(0))))) 
                                      << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual));
    __Vtemp160[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                       ? ((VL_ULL(0x1ffffffffff80) 
                                           & (((QData)((IData)(
                                                               vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                               [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                               << 0x3eU) 
                                              | (((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                  [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                  << 0x1eU) 
                                                 | (VL_ULL(0x3fffffffffffff80) 
                                                    & ((QData)((IData)(
                                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                       >> 2U))))) 
                                          | (QData)((IData)(
                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                              << 6U) 
                                                             | ((0x3cU 
                                                                 & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                     [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                     << 0x1eU) 
                                                                    | (0x3ffffffcU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 2U)))) 
                                                                | (3U 
                                                                   & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                       << 0xdU) 
                                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                         [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                         >> 0x13U))))))))
                                       : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                           ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                               << 7U) 
                                              | (QData)((IData)(
                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                  << 6U) 
                                                                 | ((0x3cU 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                         >> 
                                                                         (0xfU 
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                                                                        << 2U)) 
                                                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                           : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                               ? ((QData)((IData)(
                                                                  (0xfffffffU 
                                                                   & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                  << 7U)
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                             >> 0x1fU)) | (0xfffffffeU 
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                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                         ? 
                                                        ((VL_ULL(0x1ffffffffff80) 
                                                          & (((QData)((IData)(
                                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                              << 0x3eU) 
                                                             | (((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
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                                                                   & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                      >> 2U))))) 
                                                         | (QData)((IData)(
                                                                           (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) 
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                                                                            | ((0x3cU 
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                                                                                << 0x1eU) 
                                                                                | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                               | (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                         : 
                                                        ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                          ? 
                                                         ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
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                                                          | (QData)((IData)(
                                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) 
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                                                                             | ((0x3cU 
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                                                                                >> 
                                                                                (0xfU 
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                                                                                << 2U)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                          : 
                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                           ? 
                                                          ((QData)((IData)(
                                                                           (0xfffffffU 
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                                                                       ? 
                                                                      (1U 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                          >> 1U))
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 1U
                                                                        : 0U)) 
                                                                     << 0x1fU)) 
                                                                 | ((0x40000000U 
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                                                                         (1U 
                                                                          & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                          : 
                                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
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                                                                          (1U 
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                                                                                >> 0x1cU)))
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                                                                        << 0x1eU)) 
                                                                    | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                          ? 1U
                                                                          : 
                                                                         (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                           ? 1U
                                                                           : 
                                                                          (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                            & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                            ? 1U
                                                                            : 0U))) 
                                                                        << 0x1dU) 
                                                                       | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) 
                                                                              | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) 
                                                                            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) 
                                                                           << 0x1cU) 
                                                                          | ((0xffffffcU 
                                                                              & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
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                                                                                (0x3ffffffU 
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                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
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                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
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                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
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                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
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                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                             | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                << 0x20U) 
                                               | (QData)((IData)(
                                                                 ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                   ? 
                                                                  ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                    [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                    << 0xbU) 
                                                                   | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                      [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                      >> 0x15U))
                                                                   : 
                                                                  ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                    ? 
                                                                   (((0U 
                                                                      == 
                                                                      (0x1fU 
                                                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                          << 5U)))
                                                                      ? 0U
                                                                      : 
                                                                     (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                      ((IData)(1U) 
                                                                       + 
                                                                       (3U 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                      << 
                                                                      ((IData)(0x20U) 
                                                                       - 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                           << 5U))))) 
                                                                    | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                       (3U 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                       >> 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                           << 5U))))
                                                                    : 0U)))))) 
                                      << 0x12U)) | 
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                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
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                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U)))))) 
                                   >> 0xeU)) | (0xfffc0000U 
                                                & ((IData)(
                                                           ((((QData)((IData)(
                                                                              ((0x80000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 1U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 0U)) 
                                                                                << 0x1fU)) 
                                                                               | ((0x40000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (1U 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                                 : 0U)) 
                                                                                << 0x1eU)) 
                                                                                | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                                 ? 1U
                                                                                 : 0U))) 
                                                                                << 0x1dU) 
                                                                                | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) 
                                                                                << 0x1cU) 
                                                                                | ((0xffffffcU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                                | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                              << 0x20U) 
                                                             | (QData)((IData)(
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xbU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x15U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U)))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))
                                                                                 : 0U))))) 
                                                            >> 0x20U)) 
                                                   << 0x12U)));
    __Vtemp161[7U] = (0x3ffffU & ((IData)(((((QData)((IData)(
                                                             ((0x80000000U 
                                                               & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
                                                                        & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U))))) 
                                           >> 0x20U)) 
                                  >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]
            : 0x39U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] 
        = __Vtemp160[4U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] 
        = __Vtemp161[5U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] 
        = __Vtemp161[6U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] 
        = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                           << 0x12U)) | __Vtemp161[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) 
           | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) 
                 & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1
                    [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
               [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head 
        = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible));
    __Vtemp174[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                ? (
                                                   (VL_ULL(0x1ffffffffff80) 
                                                    & (((QData)((IData)(
                                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                        [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                        << 0x3eU) 
                                                       | (((QData)((IData)(
                                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                           [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                           << 0x1eU) 
                                                          | (VL_ULL(0x3fffffffffffff80) 
                                                             & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                >> 2U))))) 
                                                   | (QData)((IData)(
                                                                     (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                       << 6U) 
                                                                      | ((0x3cU 
                                                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                              << 0x1eU) 
                                                                             | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                         | (3U 
                                                                            & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                               | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                    ? 
                                                   ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                     << 7U) 
                                                    | (QData)((IData)(
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                        << 6U) 
                                                                       | ((0x3cU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                               >> 
                                                                               (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                              << 2U)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                    : 
                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                     ? 
                                                    ((QData)((IData)(
                                                                     (0xfffffffU 
                                                                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                     << 7U)
                                                     : VL_ULL(0))))) 
                                      << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual));
    __Vtemp174[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                       ? ((VL_ULL(0x1ffffffffff80) 
                                           & (((QData)((IData)(
                                                               vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                               [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                               << 0x3eU) 
                                              | (((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                  [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                  << 0x1eU) 
                                                 | (VL_ULL(0x3fffffffffffff80) 
                                                    & ((QData)((IData)(
                                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                       >> 2U))))) 
                                          | (QData)((IData)(
                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                              << 6U) 
                                                             | ((0x3cU 
                                                                 & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                     [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                     << 0x1eU) 
                                                                    | (0x3ffffffcU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 2U)))) 
                                                                | (3U 
                                                                   & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                       << 0xdU) 
                                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                         [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                         >> 0x13U))))))))
                                       : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                           ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                               << 7U) 
                                              | (QData)((IData)(
                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                  << 6U) 
                                                                 | ((0x3cU 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                         >> 
                                                                         (0xfU 
                                                                          & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                             << 2U))) 
                                                                        << 2U)) 
                                                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                           : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                               ? ((QData)((IData)(
                                                                  (0xfffffffU 
                                                                   & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                  << 7U)
                                               : VL_ULL(0))))) 
                             >> 0x1fU)) | (0xfffffffeU 
                                           & ((IData)(
                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                         ? 
                                                        ((VL_ULL(0x1ffffffffff80) 
                                                          & (((QData)((IData)(
                                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                              << 0x3eU) 
                                                             | (((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
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                                                                  ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                  ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                        : 
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                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) 
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                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) 
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                                                                       | ((0xffffffcU 
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                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
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                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
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                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
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                                                                                (0xfU 
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                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
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                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
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                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
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                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
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                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U)))))) 
                                   >> 0xeU)) | (0xfffc0000U 
                                                & ((IData)(
                                                           ((((QData)((IData)(
                                                                              ((0x80000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 1U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 0U)) 
                                                                                << 0x1fU)) 
                                                                               | ((0x40000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (1U 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                                 : 0U)) 
                                                                                << 0x1eU)) 
                                                                                | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                                 ? 1U
                                                                                 : 0U))) 
                                                                                << 0x1dU) 
                                                                                | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) 
                                                                                << 0x1cU) 
                                                                                | ((0xffffffcU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                                | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                              << 0x20U) 
                                                             | (QData)((IData)(
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xbU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x15U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U)))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))
                                                                                 : 0U))))) 
                                                            >> 0x20U)) 
                                                   << 0x12U)));
    __Vtemp175[7U] = (0x3ffffU & ((IData)(((((QData)((IData)(
                                                             ((0x80000000U 
                                                               & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
                                                                        & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U))))) 
                                           >> 0x20U)) 
                                  >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]
            : 0x39U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] 
        = __Vtemp174[4U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] 
        = __Vtemp175[5U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] 
        = __Vtemp175[6U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] 
        = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                           << 0x12U)) | __Vtemp175[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) 
           | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) 
                 & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1
                    [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
               [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head 
        = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible));
    __Vtemp188[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                ? (
                                                   (VL_ULL(0x1ffffffffff80) 
                                                    & (((QData)((IData)(
                                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                        [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                        << 0x3eU) 
                                                       | (((QData)((IData)(
                                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                           [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                           << 0x1eU) 
                                                          | (VL_ULL(0x3fffffffffffff80) 
                                                             & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                >> 2U))))) 
                                                   | (QData)((IData)(
                                                                     (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                       << 6U) 
                                                                      | ((0x3cU 
                                                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                              << 0x1eU) 
                                                                             | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                         | (3U 
                                                                            & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                               | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                    ? 
                                                   ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                     << 7U) 
                                                    | (QData)((IData)(
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                        << 6U) 
                                                                       | ((0x3cU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                               >> 
                                                                               (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                              << 2U)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                    : 
                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                     ? 
                                                    ((QData)((IData)(
                                                                     (0xfffffffU 
                                                                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                     << 7U)
                                                     : VL_ULL(0))))) 
                                      << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual));
    __Vtemp188[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                       ? ((VL_ULL(0x1ffffffffff80) 
                                           & (((QData)((IData)(
                                                               vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                               [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                               << 0x3eU) 
                                              | (((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                  [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                  << 0x1eU) 
                                                 | (VL_ULL(0x3fffffffffffff80) 
                                                    & ((QData)((IData)(
                                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                       >> 2U))))) 
                                          | (QData)((IData)(
                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                              << 6U) 
                                                             | ((0x3cU 
                                                                 & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                     [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                     << 0x1eU) 
                                                                    | (0x3ffffffcU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 2U)))) 
                                                                | (3U 
                                                                   & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                       << 0xdU) 
                                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                         [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                         >> 0x13U))))))))
                                       : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                           ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                               << 7U) 
                                              | (QData)((IData)(
                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                  << 6U) 
                                                                 | ((0x3cU 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                         >> 
                                                                         (0xfU 
                                                                          & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                             << 2U))) 
                                                                        << 2U)) 
                                                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                           : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                               ? ((QData)((IData)(
                                                                  (0xfffffffU 
                                                                   & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                  << 7U)
                                               : VL_ULL(0))))) 
                             >> 0x1fU)) | (0xfffffffeU 
                                           & ((IData)(
                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                         ? 
                                                        ((VL_ULL(0x1ffffffffff80) 
                                                          & (((QData)((IData)(
                                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                              << 0x3eU) 
                                                             | (((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                                 << 0x1eU) 
                                                                | (VL_ULL(0x3fffffffffffff80) 
                                                                   & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                      >> 2U))))) 
                                                         | (QData)((IData)(
                                                                           (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                             << 6U) 
                                                                            | ((0x3cU 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                               | (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                         : 
                                                        ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                          ? 
                                                         ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                           << 7U) 
                                                          | (QData)((IData)(
                                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                              << 6U) 
                                                                             | ((0x3cU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                                >> 
                                                                                (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                                << 2U)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                          : 
                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                           ? 
                                                          ((QData)((IData)(
                                                                           (0xfffffffU 
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                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
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                                                                  ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                  ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                      << 
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                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
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                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) 
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                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) 
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                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) 
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                                                                       | ((0xffffffcU 
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                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
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                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
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                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
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                                                                                (0xfU 
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                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
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                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
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                                                                                >> 
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                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 
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                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
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                                                                                >> 0x1dU)))
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                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                                (3U 
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                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
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                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
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                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
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                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
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                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
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                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
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                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U)))))) 
                                   >> 0xeU)) | (0xfffc0000U 
                                                & ((IData)(
                                                           ((((QData)((IData)(
                                                                              ((0x80000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 1U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 0U)) 
                                                                                << 0x1fU)) 
                                                                               | ((0x40000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (1U 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                                 : 0U)) 
                                                                                << 0x1eU)) 
                                                                                | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                                 ? 1U
                                                                                 : 0U))) 
                                                                                << 0x1dU) 
                                                                                | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) 
                                                                                << 0x1cU) 
                                                                                | ((0xffffffcU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                                | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                              << 0x20U) 
                                                             | (QData)((IData)(
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xbU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x15U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U)))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))
                                                                                 : 0U))))) 
                                                            >> 0x20U)) 
                                                   << 0x12U)));
    __Vtemp189[7U] = (0x3ffffU & ((IData)(((((QData)((IData)(
                                                             ((0x80000000U 
                                                               & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
                                                                        & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U))))) 
                                           >> 0x20U)) 
                                  >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]
            : 0x39U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] 
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        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
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                  >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
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                             >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) 
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                  >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                               >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) 
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                 >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
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                >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                             >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) 
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                               >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) 
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                >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
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                               >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) 
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                                                                     (__Vtemp191[
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                                                                      << 
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                                                                 (__Vtemp191[
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                                                                                (__Vtemp191[
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                                                                                << 
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                                                                                >> 
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                                                                    (__Vtemp191[
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                                                                     << 
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                                                                      (0x1fU 
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                                                                      >> 
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                                                    << 0x15U)) 
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                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
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                                                  | ((0xfffffffcU 
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                                                     | ((0xfffffffeU 
                                                         & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e) 
                                                            << 1U)) 
                                                        | (0x1ffffU 
                                                           & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c
                                                              [0U] 
                                                              >> 0xfU))))));
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                                                                       (3U 
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                                                                      << 
                                                                      ((IData)(0x20U) 
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                                                                       (0x1fU 
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                                                                       >> 
                                                                       (0x1fU 
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                                                                 (__Vtemp217[
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                                                                  << 
                                                                  ((IData)(0x20U) 
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                                                                   (0x1fU 
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                                                                   >> 
                                                                   (0x1fU 
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                                                                                (__Vtemp217[
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                                                                                (0x1fU 
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                                                                                >> 
                                                                                (0x1fU 
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                                                                    (__Vtemp217[
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                                                                     << 
                                                                     ((IData)(0x20U) 
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                                                                      (0x1fU 
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                                                                      >> 
                                                                      (0x1fU 
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                                                 | (QData)((IData)(
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                                                                          << 5U)))
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                                                                     (__Vtemp230[
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                                                                       + 
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                                                                      << 
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                                                                           << 5U))))) 
                                                                    | (__Vtemp230[
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                                             | (QData)((IData)(
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                                                                      << 5U)))
                                                                  ? 0U
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                                                                 (__Vtemp230[
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                                                                  << 
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                                                            | (QData)((IData)(
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                                                                                << 5U)))
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                                                                                (__Vtemp230[
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                                                                                << 
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                                                                               | (__Vtemp230[
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                                                                                >> 
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                                                | (QData)((IData)(
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                                                                     ? 0U
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                                                                    (__Vtemp230[
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                                                                      + 
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                                                                     << 
                                                                     ((IData)(0x20U) 
                                                                      - 
                                                                      (0x1fU 
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                                                                          << 5U))))) 
                                                                   | (__Vtemp230[
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                                                                      >> 
                                                                      (0x1fU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                          [0U] 
                                                                          << 5U))))))) 
                                               >> 0x20U)) 
                                      >> 9U)));
    __Vtemp240[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) 
                                       | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) 
                                            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
                                               [0U])) 
                                           & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                                              [0U])) 
                                          & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
                                          [0U])) << 0x19U)) 
                      | (0x1ffffffU & ((0x1000000U 
                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) 
                                           << 0x18U)) 
                                       | ((0x1800000U 
                                           & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
                                              [0U] 
                                              << 0x17U)) 
                                          | ((0x1c00000U 
                                              & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1
                                                 [0U] 
                                                 << 0x16U)) 
                                             | ((0x1e00000U 
                                                 & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) 
                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)) 
                                                    << 0x15U)) 
                                                | ((0x1f00000U 
                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                                                       [0U] 
                                                       << 0x14U)) 
                                                   | ((0x1f80000U 
                                                       & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
                                                           [0U] 
                                                           & (~ 
                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                                                              [0U])) 
                                                          << 0x13U)) 
                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                                                         [0U] 
                                                         >> 7U)))))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] 
        = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                  [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] 
        = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c
                           [0U] << 0x11U)) | (IData)(
                                                     (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                                                      [0U] 
                                                      >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] 
        = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
                           [0U][0U] << 0x17U)) | ((0xfffffff8U 
                                                   & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c
                                                      [0U] 
                                                      << 3U)) 
                                                  | ((0xfffffffcU 
                                                      & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e) 
                                                         << 2U)) 
                                                     | ((0xfffffffeU 
                                                         & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e) 
                                                            << 1U)) 
                                                        | (0x1ffffU 
                                                           & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c
                                                              [0U] 
                                                              >> 0xfU))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] 
        = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
                         [0U][0U] >> 9U)) | (0xff800000U 
                                             & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
                                                [0U][1U] 
                                                << 0x17U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] 
        = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
                         [0U][1U] >> 9U)) | (0xff800000U 
                                             & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
                                                [0U][2U] 
                                                << 0x17U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] 
        = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
                         [0U][2U] >> 9U)) | (0xff800000U 
                                             & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
                                                [0U][3U] 
                                                << 0x17U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] 
        = __Vtemp237[6U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] 
        = __Vtemp237[7U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] 
        = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                           [0U] << 0x19U)) | __Vtemp238[8U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] 
        = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
                              [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1
                              [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) 
                            & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                               << 7U) 
                                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x19U))) 
                               == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                               [0U])) << 0x1bU)) | 
           ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1
                            [0U] << 0x1aU)) | __Vtemp240[9U]));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write 
        = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                        [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
               [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e))) 
            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
               ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                           [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                          ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1
                                             [0U] >> 2U)))
                          : 0U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
               ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1
                           [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                          ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1
                                             [0U] >> 2U)))
                          : 0U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
               ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1
                           [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                          ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1
                                             [0U] >> 2U)))
                          : 0U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 4U));
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        = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
               ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                           [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                          ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                                             [0U] >> 2U)))
                          : 0U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
            [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)))
            ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
            [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)))
            ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
            [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)))
            ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
            [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)))
            ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)));
}

VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_sequent__TOP__4\n"); );
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Variables
    CData/*2:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    CData/*1:0*/ __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0;
    CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
    CData/*4:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
    CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0;
    CData/*4:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
    CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0;
    CData/*2:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    CData/*1:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0;
    CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0;
    SData/*15:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0;
    CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1;
    CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0;
    CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0;
    CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0;
    CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1;
    CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1;
    CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1;
    CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2;
    CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2;
    CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2;
    CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3;
    CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3;
    CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3;
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    CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4;
    CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4;
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    CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5;
    CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5;
    CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5;
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    CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7;
    CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7;
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    CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8;
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    CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    CData/*1:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0;
    CData/*2:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    CData/*1:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0;
    CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0;
    SData/*15:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    SData/*15:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    SData/*15:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    SData/*15:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    WData/*115:0*/ __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[4];
    WData/*153:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[5];
    WData/*313:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[10];
    IData/*19:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0;
    WData/*84:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[3];
    WData/*75:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[3];
    WData/*199:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[7];
    WData/*153:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[5];
    WData/*313:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[10];
    IData/*19:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0;
    WData/*84:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[3];
    WData/*75:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[3];
    WData/*199:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[7];
    WData/*153:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[5];
    WData/*313:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[10];
    IData/*19:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0;
    WData/*84:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[3];
    WData/*75:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[3];
    WData/*199:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[7];
    WData/*153:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[5];
    WData/*313:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[10];
    IData/*19:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0;
    WData/*84:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[3];
    WData/*75:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[3];
    WData/*199:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[7];
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    WData/*95:0*/ __Vtemp277[3];
    WData/*95:0*/ __Vtemp278[3];
    WData/*95:0*/ __Vtemp279[3];
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    WData/*255:0*/ __Vtemp402[8];
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    WData/*287:0*/ __Vtemp454[9];
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    QData/*54:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0;
    QData/*54:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0;
    QData/*54:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0;
    QData/*54:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0;
    // Body
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
    __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r;
    __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U;
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U;
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U;
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U;
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U;
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U;
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U;
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U;
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U;
        }
    }
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U;
    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 0U;
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                                            | (QData)((IData)(
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                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[3U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
                                 >> 0xaU));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen 
                = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                              >> 2U));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                = (VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[0U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[1U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[2U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[3U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
                                 >> 0xaU));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen 
                = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                              >> 2U));
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) {
            vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr 
                = (0xfffffffU & ((IData)(0x10U) + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw 
                = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                           >> 0x12U));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] 
                = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                 << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
                                              >> 0xaU)));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw 
                = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                           >> 0x12U));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] 
                = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                 << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
                                              >> 0xaU)));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw 
                = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                           >> 0x12U));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] 
                = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                 << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
                                              >> 0xaU)));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw 
                = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                           >> 0x12U));
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] 
                = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
                    << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
                                 >> 0xaU));
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] 
                = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                 << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
                                              >> 0xaU)));
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] = 0U;
    } else {
        if (((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) 
             & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))) {
            vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] 
                = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U];
            vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] 
                = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[1U];
            vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] 
                = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[2U];
            vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] 
                = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U];
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0);
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) 
                                - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0);
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0);
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) 
                                - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0);
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0);
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) 
                                - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0);
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0);
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) 
                                - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U];
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original = 0U;
    } else {
        if ((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use))) {
            vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original 
                = vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid;
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid = 0U;
    } else {
        if (((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) 
             & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))) {
            vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid 
                = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) 
                   & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids 
                = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                            >> 0x16U) & VL_NEGATE_I((IData)(
                                                            (1U 
                                                             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))));
        } else {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop) {
                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids 
                    = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) 
                       & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids));
            }
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids 
                = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                            >> 0x16U) & VL_NEGATE_I((IData)(
                                                            (1U 
                                                             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))));
        } else {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop) {
                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids 
                    = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) 
                       & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids));
            }
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids 
                = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                            >> 0x16U) & VL_NEGATE_I((IData)(
                                                            (1U 
                                                             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))));
        } else {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop) {
                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids 
                    = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) 
                       & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids));
            }
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids 
                = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                            >> 0x16U) & VL_NEGATE_I((IData)(
                                                            (1U 
                                                             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))));
        } else {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop) {
                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids 
                    = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) 
                       & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids));
            }
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) 
                                - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) 
                                - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) 
                                - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) 
                                - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U;
    } else {
        if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) 
                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
            }
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) {
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) 
                                - (IData)(1U)));
            }
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U;
    } else {
        if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) 
                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
            }
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) {
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) 
                                - (IData)(1U)));
            }
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U;
    } else {
        if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) 
                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
            }
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) {
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) 
                                - (IData)(1U)));
            }
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U;
    } else {
        if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) 
                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
                    = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
            }
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) {
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
                    = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) 
                                - (IData)(1U)));
            }
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) {
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) {
                if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq))) {
                    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
                        = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) 
                                   - (IData)(1U)));
                }
            }
        }
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) {
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) {
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) {
                if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq))) {
                    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
                        = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) 
                                   - (IData)(1U)));
                }
            }
        }
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) {
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) {
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) {
                if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq))) {
                    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
                        = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) 
                                   - (IData)(1U)));
                }
            }
        }
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) {
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) {
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) {
                if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq))) {
                    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
                        = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) 
                                   - (IData)(1U)));
                }
            }
        }
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) {
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
                = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U];
            __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U];
        if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) 
                    & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                   | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) 
                      << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)));
        }
        if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) {
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) 
                               | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
                              | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) 
                                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                                 << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))));
        }
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) {
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) 
                   & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) 
                    & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                   | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) 
                      << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)));
        }
        if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) {
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) 
                               | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
                              | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) 
                                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                                 << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))));
        }
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) {
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) 
                   & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) 
                    & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                   | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) 
                      << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)));
        }
        if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) {
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) 
                               | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
                              | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) 
                                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                                 << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))));
        }
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) {
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) 
                   & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) 
                    & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                   | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) 
                      << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)));
        }
        if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) {
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) 
                               | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
                              | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) 
                                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                                 << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))));
        }
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) {
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
                = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) 
                   & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table));
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U];
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U];
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U];
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U];
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U;
    } else {
        if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
               >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                         >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire) 
                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)))) {
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
                = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U;
    } else {
        if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
               >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                         >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire) 
                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)))) {
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
                = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U;
    } else {
        if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
               >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                         >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire) 
                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)))) {
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
                = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U;
    } else {
        if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
               >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                         >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire) 
                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)))) {
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
                = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)));
        }
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U];
    }
    if (vlTOPp->reset) {
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing) {
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U];
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) {
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U;
                if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) {
                    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U;
                }
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
                    = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
                = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U];
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) {
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
            if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) {
                if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) {
                    if (Verilated::assertOn()) {
                        if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) 
                                         != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) {
                            VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n",
                                      64,VL_TIME_Q(),
                                      vlSymsp->name());
                            VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, "");
                        }
                    }
                    __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U;
                }
                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U;
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
                    = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) 
                             - (IData)(1U)));
            }
            __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
                = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)));
        }
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r 
            = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing) 
               & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) 
                  | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) 
                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading))));
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
               : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] 
            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
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            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
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            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
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            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
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            = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data
            [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)
               ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)
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    if ((1U & (~ (IData)(vlTOPp->reset)))) {
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                                              | (0x3fe00000U 
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                                                    >> 2U)))) 
                              | (IData)(((((QData)((IData)(
                                                           (3U 
                                                            & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) 
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                                          | ((VL_ULL(0x7fffffffffe00) 
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                                                 | (VL_ULL(0xfffffffffffffe00) 
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                                             | (QData)((IData)(
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                                                                | ((0xf0U 
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                                                                   | ((0xcU 
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                                                                          | (0x7fcU 
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                                                                                >> 0x15U)))) 
                                                                      | (3U 
                                                                         & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                                            >> 0x16U))))))))) 
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            __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] 
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                                          & (((QData)((IData)(
                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                              << 0x22U) 
                                             | (VL_ULL(0xfffffffffffffe00) 
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                                         | (QData)((IData)(
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                                                            | ((0xf0U 
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                                                               | ((0xcU 
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                                                                      | (0x7fcU 
                                                                         & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                                            >> 0x15U)))) 
                                                                  | (3U 
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                                                                        >> 0x16U))))))))));
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            __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U;
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    if ((1U & (~ (IData)(vlTOPp->reset)))) {
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                                              | (0x3fe00000U 
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                                                    >> 2U)))) 
                              | (IData)(((((QData)((IData)(
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                                          | ((VL_ULL(0x7fffffffffe00) 
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                                                  << 0x22U) 
                                                 | (VL_ULL(0xfffffffffffffe00) 
                                                    & ((QData)((IData)(
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                                             | (QData)((IData)(
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                                                                | ((0xf0U 
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                                                                   | ((0xcU 
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                                                                           << 0xbU) 
                                                                          | (0x7fcU 
                                                                             & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                                                >> 0x15U)))) 
                                                                      | (3U 
                                                                         & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                                            >> 0x16U))))))))) 
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            __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] 
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                            << 0x33U) | ((VL_ULL(0x7fffffffffe00) 
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                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                              << 0x22U) 
                                             | (VL_ULL(0xfffffffffffffe00) 
                                                & ((QData)((IData)(
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                                                   << 2U)))) 
                                         | (QData)((IData)(
                                                           ((0x100U 
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                                                            | ((0xf0U 
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                                                               | ((0xcU 
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                                                                      | (0x7fcU 
                                                                         & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                                            >> 0x15U)))) 
                                                                  | (3U 
                                                                     & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                                        >> 0x16U))))))))));
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                = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
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            __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U;
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    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
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                                              | (0x3fe00000U 
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                                                    >> 2U)))) 
                              | (IData)(((((QData)((IData)(
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                                          | ((VL_ULL(0x7fffffffffe00) 
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                                                 | (VL_ULL(0xfffffffffffffe00) 
                                                    & ((QData)((IData)(
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                                                       << 2U)))) 
                                             | (QData)((IData)(
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                                                                | ((0xf0U 
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                                                                   | ((0xcU 
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                                                                          | (0x7fcU 
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                                                                                >> 0x15U)))) 
                                                                      | (3U 
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                                         >> 0x20U)));
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                                              << 0x22U) 
                                             | (VL_ULL(0xfffffffffffffe00) 
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                                         | (QData)((IData)(
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                                                            | ((0xf0U 
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                                                                   << 2U)) 
                                                               | ((0xcU 
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                                                                       << 0xbU) 
                                                                      | (0x7fcU 
                                                                         & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                                            >> 0x15U)))) 
                                                                  | (3U 
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                                                                        >> 0x16U))))))))));
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                = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
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                                               << 0x1eU) 
                                              | (0x3fe00000U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
                                                    >> 2U)))) 
                              | (IData)(((((QData)((IData)(
                                                           (3U 
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                                           << 0x33U) 
                                          | ((VL_ULL(0x7fffffffffe00) 
                                              & (((QData)((IData)(
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                                                  << 0x22U) 
                                                 | (VL_ULL(0xfffffffffffffe00) 
                                                    & ((QData)((IData)(
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                                                       << 2U)))) 
                                             | (QData)((IData)(
                                                               ((0x100U 
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                                                                    << 2U)) 
                                                                | ((0xf0U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                                                       << 2U)) 
                                                                   | ((0xcU 
                                                                       & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                                           << 0xbU) 
                                                                          | (0x7fcU 
                                                                             & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                                                >> 0x15U)))) 
                                                                      | (3U 
                                                                         & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                                            >> 0x16U))))))))) 
                                         >> 0x20U)));
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] 
                = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) 
                            << 0x33U) | ((VL_ULL(0x7fffffffffe00) 
                                          & (((QData)((IData)(
                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                              << 0x22U) 
                                             | (VL_ULL(0xfffffffffffffe00) 
                                                & ((QData)((IData)(
                                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                   << 2U)))) 
                                         | (QData)((IData)(
                                                           ((0x100U 
                                                             & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                                                << 2U)) 
                                                            | ((0xf0U 
                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                                                   << 2U)) 
                                                               | ((0xcU 
                                                                   & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                                       << 0xbU) 
                                                                      | (0x7fcU 
                                                                         & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                                            >> 0x15U)))) 
                                                                  | (3U 
                                                                     & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                                        >> 0x16U))))))))));
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] 
                = __Vtemp279[1U];
            __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] 
                = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                >> 2U));
            __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U;
            __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table 
                = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                   | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)));
        } else {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) {
                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table 
                    = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) 
                       & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table));
                __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
                    = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr)));
            }
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table 
                = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                   | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)));
        } else {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) {
                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table 
                    = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) 
                       & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table));
                __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
                    = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr)));
            }
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table 
                = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                   | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)));
        } else {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) {
                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table 
                    = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) 
                       & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table));
                __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
                    = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr)));
            }
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U;
        __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table 
                = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                   | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)));
        } else {
            if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) {
                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table 
                    = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) 
                       & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table));
                __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
                    = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr)));
            }
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffffffe) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffffffd) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffffffb) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffffff7) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffffffef) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffffffdf) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffffffbf) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffffff7f) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffffeff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffffdff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffffbff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffff7ff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffffefff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffffdfff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffffbfff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffff7fff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffeffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffdffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffffbffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffff7ffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffefffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffdfffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffffbfffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffff7fffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffeffffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffdffffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffffbffffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xfffffffff7ffffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffefffffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffdfffffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffffbfffffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
            = (VL_ULL(0xffffffff7fffffff) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid);
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                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 
                    = (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                                   [0U] >> 6U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 
                    = (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                                   [0U] >> 6U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 
                    = (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                                   [0U] >> 6U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 
                    = (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                                   [0U] >> 6U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 
                = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                  << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                            >> 0x19U)));
            if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) 
                                      * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) {
                VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1);
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 
                = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                  << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                            >> 0x19U)));
            if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) 
                                      * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) {
                VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1);
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 
                = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                  << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                            >> 0x19U)));
            if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) 
                                      * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) {
                VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1);
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 
                = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                  << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                            >> 0x19U)));
            if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) 
                                      * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) {
                VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1);
            }
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U];
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U];
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U];
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U];
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 
                    = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                        ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                                [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                                  [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            } else {
                if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e) {
                    __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U;
                    __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 
                        = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                           [0U]);
                }
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 
                    = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                        ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                                [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                                  [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            } else {
                if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e) {
                    __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U;
                    __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 
                        = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                           [0U]);
                }
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 
                    = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                        ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                                [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                                  [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            } else {
                if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e) {
                    __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U;
                    __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 
                        = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                           [0U]);
                }
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 
                    = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                        ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                                [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                                  [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            } else {
                if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) {
                    __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U;
                    __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 
                        = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                           [0U]);
                }
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U;
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                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 
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                       [0U]);
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            if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
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                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U;
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                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U;
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                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 8U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 0x10U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 0x18U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 8U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 0x10U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 0x18U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
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            if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 8U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 0x10U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 0x18U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
        }
    }
    if ((1U & (~ (IData)(vlTOPp->reset)))) {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                              >> 8U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                              >> 0x10U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 
                    = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                 << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
                                           >> 0x18U)));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 
                    = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]);
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 8U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 0x10U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
            if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) {
                __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 
                    = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
                                >> 0x18U));
                __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U;
                __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U;
                __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 
                    = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                       [0U]);
            }
        }
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U];
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    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U];
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    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U];
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    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[3U];
    }
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U];
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U];
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U];
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U];
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U];
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr 
        = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] 
            = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U;
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15], __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15);
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        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15], __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12);
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    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14);
    }
    if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15) {
        VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15), 
                          vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
                          [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15);
    }
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use 
        = (((0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid)) 
            | (0U == ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid) 
                      - (IData)(1U)))) & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r));
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r = 0U;
    } else {
        if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing) {
            vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r 
                = vlTOPp->dram_req_addr;
        }
    }
    vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = 
        ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) 
         | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                  << 3U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = 
        ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) 
         | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                  << 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = 
        ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) 
         | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                  << 1U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = 
        ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) 
         | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]);
    vlTOPp->VX_cache__DOT__per_bank_core_req_ready 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) 
           | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 3U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]);
    vlTOPp->VX_cache__DOT__per_bank_core_req_ready 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) 
           | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]);
    vlTOPp->VX_cache__DOT__per_bank_core_req_ready 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) 
           | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 1U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]);
    vlTOPp->VX_cache__DOT__per_bank_core_req_ready 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) 
           | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use 
        = ((IData)(vlTOPp->reset) ? 0U : ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill)
                                           ? (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
                                           : (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->__Vtableidx8 = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index 
        = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index
        [vlTOPp->__Vtableidx8];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request 
        = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request
        [vlTOPp->__Vtableidx8];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx8];
    vlTOPp->__Vtableidx7 = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index 
        = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index
        [vlTOPp->__Vtableidx7];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request 
        = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request
        [vlTOPp->__Vtableidx7];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx7];
    vlTOPp->__Vtableidx6 = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index 
        = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index
        [vlTOPp->__Vtableidx6];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request 
        = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request
        [vlTOPp->__Vtableidx6];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx6];
    vlTOPp->__Vtableidx5 = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index 
        = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index
        [vlTOPp->__Vtableidx5];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request 
        = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request
        [vlTOPp->__Vtableidx5];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx5];
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) 
           | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 3U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) 
           | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) 
           | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) 
                    << 1U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) 
           | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U]
            : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                 [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                 >> 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                 [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                 >> 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                 [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                 >> 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                 [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                 >> 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible 
        = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible 
        = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible 
        = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible 
        = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) 
                  & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)));
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U];
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U];
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U];
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U;
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U;
    } else {
        if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) {
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U];
            vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U];
        }
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
            << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                        >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0U] 
        = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                  << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                              >> 0x12U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0U] 
        = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)(
                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) 
                                       << 0x3fU) | 
                                      (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) 
                                        << 0x1fU) | 
                                       ((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) 
                                        >> 1U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x10U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x11U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0U] 
        = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0U] 
        = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                          << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                                      >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
            << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                        >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0U] 
        = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                  << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                              >> 0x12U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0U] 
        = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)(
                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) 
                                       << 0x3fU) | 
                                      (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) 
                                        << 0x1fU) | 
                                       ((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) 
                                        >> 1U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x10U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x11U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0U] 
        = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0U] 
        = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                          << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                                      >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
            << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                        >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0U] 
        = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                  << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                              >> 0x12U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0U] 
        = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)(
                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) 
                                       << 0x3fU) | 
                                      (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) 
                                        << 0x1fU) | 
                                       ((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) 
                                        >> 1U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x10U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x11U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0U] 
        = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0U] 
        = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                          << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                                      >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
            << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] 
                        >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0U] 
        = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                  << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                              >> 0x12U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0U] 
        = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)(
                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) 
                                       << 0x3fU) | 
                                      (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) 
                                        << 0x1fU) | 
                                       ((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) 
                                        >> 1U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x10U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x11U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0x12U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0U] 
        = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                 >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0U] 
        = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] 
                          << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] 
                                      >> 0x14U)));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty 
        = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                            >> 0x16U))))) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty 
        = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                            >> 0x16U))))) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty 
        = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                            >> 0x16U))))) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty 
        = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] 
                                            >> 0x16U))))) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) 
           | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) 
           | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                    << 1U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) 
           | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                    << 2U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) 
           | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                    << 3U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U];
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = 
        ((0x3fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) 
         | (0xc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
                     >> 4U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
        = ((0x3fffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) 
           | (0xc0000000U & ((IData)((VL_ULL(0x3ffffffffff) 
                                      & (((QData)((IData)(
                                                          vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                          << 0x20U) 
                                         | (QData)((IData)(
                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                             << 0x1eU)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] 
        = ((0x3fffffffU & ((IData)((VL_ULL(0x3ffffffffff) 
                                    & (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                        << 0x20U) | (QData)((IData)(
                                                                    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                           >> 2U)) | (0xc0000000U & 
                                      ((IData)(((VL_ULL(0x3ffffffffff) 
                                                 & (((QData)((IData)(
                                                                     vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                                     << 0x20U) 
                                                    | (QData)((IData)(
                                                                      vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) 
                                                >> 0x20U)) 
                                       << 0x1eU)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] 
        = (0x3fffffffU & ((IData)(((VL_ULL(0x3ffffffffff) 
                                    & (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                        << 0x20U) | (QData)((IData)(
                                                                    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) 
                                   >> 0x20U)) >> 2U));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U];
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = 
        ((0xcfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) 
         | (0x30U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
                     >> 6U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
        = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) 
           | (0xfff00000U & ((IData)((VL_ULL(0x3ffffffffff) 
                                      & (((QData)((IData)(
                                                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                          << 0x20U) 
                                         | (QData)((IData)(
                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                             << 0x14U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
        = ((0xc0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) 
           | ((0xfffffU & ((IData)((VL_ULL(0x3ffffffffff) 
                                    & (((QData)((IData)(
                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                        << 0x20U) | (QData)((IData)(
                                                                    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                           >> 0xcU)) | (0xfff00000U 
                                        & ((IData)(
                                                   ((VL_ULL(0x3ffffffffff) 
                                                     & (((QData)((IData)(
                                                                         vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                                         << 0x20U) 
                                                        | (QData)((IData)(
                                                                          vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) 
                                                    >> 0x20U)) 
                                           << 0x14U))));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U];
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = 
        ((0xf3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) 
         | (0xcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
                    >> 8U)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] 
        = ((0x3ffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) 
           | (0xfffffc00U & ((IData)((VL_ULL(0x3ffffffffff) 
                                      & (((QData)((IData)(
                                                          vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                          << 0x20U) 
                                         | (QData)((IData)(
                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
        = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) 
           | ((0x3ffU & ((IData)((VL_ULL(0x3ffffffffff) 
                                  & (((QData)((IData)(
                                                      vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                      << 0x20U) | (QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) 
                         >> 0x16U)) | (0xfffffc00U 
                                       & ((IData)((
                                                   (VL_ULL(0x3ffffffffff) 
                                                    & (((QData)((IData)(
                                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                                        << 0x20U) 
                                                       | (QData)((IData)(
                                                                         vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) 
                                                   >> 0x20U)) 
                                          << 0xaU))));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U];
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = 
        ((0xfcU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) 
         | (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] 
                  >> 0xaU)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U] 
        = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] 
        = ((0xfffffc00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) 
           | (IData)(((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                                 vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) 
                                                 << 0x20U) 
                                                | (QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) 
                      >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 
        = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
            ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
                                ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                        ((IData)(1U) 
                                         + (3U & (((IData)(0x1eU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                                  >> 5U)))] 
                                        << ((IData)(0x20U) 
                                            - (0x1fU 
                                               & ((IData)(0x1eU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) 
                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                 (3U & (((IData)(0x1eU) 
                                         * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                        >> 5U))] >> 
                                 (0x1fU & ((IData)(0x1eU) 
                                           * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 
        = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
            ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
                                ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                        ((IData)(1U) 
                                         + (3U & (((IData)(0x1eU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                                  >> 5U)))] 
                                        << ((IData)(0x20U) 
                                            - (0x1fU 
                                               & ((IData)(0x1eU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) 
                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                 (3U & (((IData)(0x1eU) 
                                         * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                        >> 5U))] >> 
                                 (0x1fU & ((IData)(0x1eU) 
                                           * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 
        = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
            ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
                                ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                        ((IData)(1U) 
                                         + (3U & (((IData)(0x1eU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                                  >> 5U)))] 
                                        << ((IData)(0x20U) 
                                            - (0x1fU 
                                               & ((IData)(0x1eU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) 
                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                 (3U & (((IData)(0x1eU) 
                                         * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                        >> 5U))] >> 
                                 (0x1fU & ((IData)(0x1eU) 
                                           * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) 
                 >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 
        = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
            ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))
                                ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                        ((IData)(1U) 
                                         + (3U & (((IData)(0x1eU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                                  >> 5U)))] 
                                        << ((IData)(0x20U) 
                                            - (0x1fU 
                                               & ((IData)(0x1eU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) 
                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[
                                 (3U & (((IData)(0x1eU) 
                                         * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) 
                                        >> 5U))] >> 
                                 (0x1fU & ((IData)(0x1eU) 
                                           * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
            : 0U);
    vlTOPp->dram_rsp_ready = (0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U] 
        = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[1U] 
        = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[2U] 
        = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))
            ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U]
            : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U] 
        = (0xffffU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))
                       ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U]
                       : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid 
        = (0xfU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))
                    ? ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid) 
                       & VL_NEGATE_I((IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)))))
                    : ((vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] 
                        >> 0x10U) & VL_NEGATE_I((IData)(
                                                        (1U 
                                                         & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))))));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] 
        = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) 
           | (0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                             << 0x14U)));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] 
        = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                      >> 0xcU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen 
        = ((VL_ULL(0xffffffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) 
           | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                           << 0xaU) 
                                          | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                             >> 0x16U))))) 
              << 0x30U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xcU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xdU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xeU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xfU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] 
        = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) 
           | (0xfff00000U & (0x300000U | (0xffc00000U 
                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                              << 0x1aU) 
                                             | (0x3c00000U 
                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
                                                   >> 6U)))))));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] 
        = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                      >> 6U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] 
        = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) 
           | (0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                             << 0x18U)));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] 
        = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) 
           | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                          >> 8U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen 
        = ((VL_ULL(0xffff0000ffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) 
           | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                           << 0xaU) 
                                          | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                             >> 0x16U))))) 
              << 0x20U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[8U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[9U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xaU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xbU] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] 
        = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) 
           | (0xff000000U & (0x2000000U | (0xfc000000U 
                                           & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                               << 0x1eU) 
                                              | (0x3c000000U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
                                                    >> 2U)))))));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] 
        = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) 
           | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                          >> 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] 
        = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) 
           | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                             << 0x1cU)));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] 
        = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) 
           | (0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                           >> 4U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen 
        = ((VL_ULL(0xffffffff0000ffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) 
           | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                           << 0xaU) 
                                          | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                             >> 0x16U))))) 
              << 0x10U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[4U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[5U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[6U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[7U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] 
        = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) 
           | (0xf0000000U & (0x10000000U | (0xc0000000U 
                                            & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
                                               << 2U)))));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] 
        = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) 
           | (0xffffffU & ((0xffffffcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                          << 2U)) | 
                           (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
                                  >> 0x1eU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] 
        = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) 
           | (0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U]));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen 
        = ((VL_ULL(0xffffffffffff0000) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) 
           | (IData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                          << 0xaU) 
                                         | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                                            >> 0x16U))))));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[1U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[2U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[3U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
            << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] 
                      >> 0x1cU));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] 
        = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) 
           | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] 
                             << 6U) | (0x3cU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] 
                                                >> 0x1aU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                     >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                                    >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) 
                 & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) 
                 & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) 
                 & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) 
                 & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 0U;
    if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
        [0U]) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 1U;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
               ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) 
                        == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                        [0U])) : 0U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         << 6U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] 
                                                   >> 0x1aU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                         << 0xcU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         >> 0x14U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                         << 0x12U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                           >> 0xeU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                         << 0x18U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                           >> 8U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 0x1eU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                           >> 2U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 4U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                                   >> 0x1cU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 6U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                         << 0xaU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         >> 0x16U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 7U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                         << 0x10U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                           >> 0x10U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                         << 0x16U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                           >> 0xaU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 9U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 0x1cU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                           >> 4U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xaU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 2U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                                   >> 0x1eU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xbU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         << 8U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                                   >> 0x18U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                         << 0xeU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         >> 0x12U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xdU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                         << 0x14U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                           >> 0xcU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                        >> 6U)) == 
                         vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
          [0U])][0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
          [0U])][1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
          [0U])][2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
          [0U])][3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
        = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                             [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag
           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
             [0U])]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
        = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
                              >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                                  [0U]))) << 5U)) | 
           ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty 
                               >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                                   [0U]))) << 4U)) 
            | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                             [0U])] >> 0xcU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 0U;
    if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
        [0U]) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 1U;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
               ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) 
                        == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                        [0U])) : 0U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         << 6U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] 
                                                   >> 0x1aU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                         << 0xcU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         >> 0x14U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                         << 0x12U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                           >> 0xeU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                         << 0x18U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                           >> 8U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 0x1eU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                           >> 2U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 4U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                                   >> 0x1cU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 6U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                         << 0xaU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         >> 0x16U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 7U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                         << 0x10U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                           >> 0x10U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                         << 0x16U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                           >> 0xaU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 9U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 0x1cU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                           >> 4U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xaU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 2U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                                   >> 0x1eU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xbU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         << 8U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                                   >> 0x18U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                         << 0xeU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         >> 0x12U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xdU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                         << 0x14U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                           >> 0xcU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                        >> 6U)) == 
                         vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
          [0U])][0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
          [0U])][1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
          [0U])][2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
          [0U])][3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
        = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                             [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag
           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
             [0U])]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
        = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
                              >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                                  [0U]))) << 5U)) | 
           ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty 
                               >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                                   [0U]))) << 4U)) 
            | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                             [0U])] >> 0xcU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 0U;
    if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
        [0U]) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 1U;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
               ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) 
                        == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                        [0U])) : 0U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         << 6U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] 
                                                   >> 0x1aU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                         << 0xcU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         >> 0x14U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                         << 0x12U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                           >> 0xeU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                         << 0x18U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                           >> 8U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 0x1eU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                           >> 2U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 4U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                                   >> 0x1cU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 6U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                         << 0xaU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         >> 0x16U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 7U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                         << 0x10U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                           >> 0x10U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                         << 0x16U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                           >> 0xaU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 9U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 0x1cU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                           >> 4U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xaU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 2U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                                   >> 0x1eU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xbU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         << 8U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                                   >> 0x18U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                         << 0xeU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         >> 0x12U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xdU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                         << 0x14U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                           >> 0xcU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                        >> 6U)) == 
                         vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
          [0U])][0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
          [0U])][1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
          [0U])][2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
          [0U])][3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
        = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                             [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag
           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
             [0U])]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
        = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
                              >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                                  [0U]))) << 5U)) | 
           ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty 
                               >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                                   [0U]))) << 4U)) 
            | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                             [0U])] >> 0xcU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 0U;
    if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
        [0U]) {
        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 1U;
    }
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
               ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) 
                        == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                        [0U])) : 0U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         << 6U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] 
                                                   >> 0x1aU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                         << 0xcU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] 
                                         >> 0x14U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                         << 0x12U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] 
                                           >> 0xeU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                         << 0x18U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] 
                                           >> 8U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 0x1eU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                           >> 2U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         << 4U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] 
                                                   >> 0x1cU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 6U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                         << 0xaU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] 
                                         >> 0x16U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 7U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                         << 0x10U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] 
                                           >> 0x10U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                         << 0x16U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] 
                                           >> 0xaU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 9U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 0x1cU) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                           >> 4U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xaU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                         << 2U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] 
                                                   >> 0x1eU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xbU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         << 8U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] 
                                                   >> 0x18U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                         << 0xeU) | 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] 
                                         >> 0x12U))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xdU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                         << 0x14U) 
                                        | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] 
                                           >> 0xcU))) 
                         == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
           | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table))
                ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] 
                                        >> 6U)) == 
                         vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                         [0U])) : 0U) << 0xfU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
          [0U])][0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
          [0U])][1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
          [0U])][2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data
        [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
          [0U])][3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
        = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                             [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag
           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
             [0U])]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
        = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid 
                              >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                                  [0U]))) << 5U)) | 
           ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty 
                               >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                                   [0U]))) << 4U)) 
            | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb
                           [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                             [0U])] >> 0xcU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) 
                 & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) 
                 & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) 
                 & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual 
        = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) 
                 & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill 
        = (0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use));
    vlTOPp->__Vtableidx3 = vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use;
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index 
        = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index
        [vlTOPp->__Vtableidx3];
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid 
        = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid
        [vlTOPp->__Vtableidx3];
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx3];
    vlTOPp->__Vtableidx1 = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index 
        = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index
        [vlTOPp->__Vtableidx1];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request 
        = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request
        [vlTOPp->__Vtableidx1];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx1];
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = 
        ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) 
         | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) 
            << 3U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) 
              << 3U));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = 
        ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) 
         | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) 
            << 2U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) 
              << 2U));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = 
        ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) 
         | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) 
            << 1U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) 
              << 1U));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = 
        ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) 
         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
            << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                      >> 0x17U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] 
        = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                             << 0x39U) 
                                            | (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                << 0x19U) 
                                               | ((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                  >> 7U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] 
        = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                      << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) 
                                            & (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                                << 0x39U) 
                                               | (((QData)((IData)(
                                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                   << 0x19U) 
                                                  | ((QData)((IData)(
                                                                     vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                     >> 7U)))) 
                                           >> 0x20U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] 
        = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) 
           | (0xfff00000U & (0x300000U | (0xffc00000U 
                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                              << 0x1dU) 
                                             | (0x1fc00000U 
                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                   >> 3U)))))));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] 
        = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                      >> 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                    >> 2U))) & (~ (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x14U))) 
                 & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                       >> 0x17U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                 >> 0x18U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                 >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                            >> 1U)) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x15U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                   >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                  >> 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
            << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                      >> 0x17U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] 
        = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                             << 0x39U) 
                                            | (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                << 0x19U) 
                                               | ((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                  >> 7U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] 
        = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                      << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) 
                                            & (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                                << 0x39U) 
                                               | (((QData)((IData)(
                                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                   << 0x19U) 
                                                  | ((QData)((IData)(
                                                                     vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                     >> 7U)))) 
                                           >> 0x20U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] 
        = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) 
           | (0xff000000U & (0x2000000U | (0xfc000000U 
                                           & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                              << 1U)))));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] 
        = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) 
           | (0xfffffU & ((0xfffffeU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                        << 1U)) | (1U 
                                                   & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                      >> 0x1fU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                    >> 2U))) & (~ (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x14U))) 
                 & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                       >> 0x17U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                 >> 0x18U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                 >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                            >> 1U)) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x15U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                   >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                  >> 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
            << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                      >> 0x17U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] 
        = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                             << 0x39U) 
                                            | (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                << 0x19U) 
                                               | ((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                  >> 7U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] 
        = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                      << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) 
                                            & (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                                << 0x39U) 
                                               | (((QData)((IData)(
                                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                   << 0x19U) 
                                                  | ((QData)((IData)(
                                                                     vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                     >> 7U)))) 
                                           >> 0x20U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] 
        = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) 
           | (0xf0000000U & (0x10000000U | (0xc0000000U 
                                            & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                               << 5U)))));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] 
        = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) 
           | (0xffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                          << 5U)) | 
                           (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                     >> 0x1bU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                    >> 2U))) & (~ (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x14U))) 
                 & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                       >> 0x17U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                 >> 0x18U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                 >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                            >> 1U)) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x15U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                   >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                  >> 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] 
            << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                      >> 0x17U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] 
        = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)(
                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                             << 0x39U) 
                                            | (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                << 0x19U) 
                                               | ((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                  >> 7U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] 
        = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                      << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) 
                                            & (((QData)((IData)(
                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) 
                                                << 0x39U) 
                                               | (((QData)((IData)(
                                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) 
                                                   << 0x19U) 
                                                  | ((QData)((IData)(
                                                                     vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) 
                                                     >> 7U)))) 
                                           >> 0x20U)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] 
        = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) 
           | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                             << 9U) | (0x1fcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x17U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                    >> 2U))) & (~ (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x14U))) 
                 & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                       >> 0x17U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                 >> 0x18U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in 
        = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                 >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                            >> 1U)) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x15U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                   >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                  >> 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
              & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
             & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
              [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] 
        = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                       << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
                                   >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] 
        = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
              & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
             & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
              [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] 
        = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                       << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
                                   >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] 
        = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
              & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
             & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
              [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] 
        = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                       << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
                                   >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] 
        = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
              & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
             & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) 
            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
              [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready 
        = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) 
           | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] 
        = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                       << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] 
                                   >> 0x14U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] 
        = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] 
        = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] 
                 >> 5U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] 
        = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->core_rsp_tag = ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                             ? (VL_ULL(0x3ffffffffff) 
                                & (((0U == (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                     ? VL_ULL(0) : 
                                    ((QData)((IData)(
                                                     vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                     ((IData)(2U) 
                                                      + 
                                                      (7U 
                                                       & (((IData)(0x2aU) 
                                                           * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                          >> 5U)))])) 
                                     << ((IData)(0x40U) 
                                         - (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                   | (((QData)((IData)(
                                                       vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                       ((IData)(1U) 
                                                        + 
                                                        (7U 
                                                         & (((IData)(0x2aU) 
                                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                            >> 5U)))])) 
                                       << ((0U == (0x1fU 
                                                   & ((IData)(0x2aU) 
                                                      * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                            ? 0x20U
                                            : ((IData)(0x20U) 
                                               - (0x1fU 
                                                  & ((IData)(0x2aU) 
                                                     * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                      | ((QData)((IData)(
                                                         vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                         (7U 
                                                          & (((IData)(0x2aU) 
                                                              * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                             >> 5U))])) 
                                         >> (0x1fU 
                                             & ((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))))
                             : VL_ULL(0));
    vlTOPp->core_rsp_valid = 0U;
    if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
         & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) 
            == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                    * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                 ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) 
                                               * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                               ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                       ((IData)(1U) 
                                        + (7U & (((IData)(0x2aU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                 >> 5U)))] 
                                       << ((IData)(0x20U) 
                                           - (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                             | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                (7U & (((IData)(0x2aU) 
                                        * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                       >> 5U))] >> 
                                (0x1fU & ((IData)(0x2aU) 
                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                 : 0U)))) {
        vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) 
                                  | ((IData)(1U) << 
                                     (3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid))));
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                               << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] 
                                            >> 0xaU))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) 
                                  | ((IData)(1U) << 
                                     (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                            >> 2U))));
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                               << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                                           >> 0x14U))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) 
                                  | ((IData)(1U) << 
                                     (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                            >> 4U))));
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] 
                               << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                                         >> 0x1eU))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) 
                                  | ((IData)(1U) << 
                                     (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                            >> 6U))));
    }
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U] = 0U;
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U;
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U;
    vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U] = 0U;
    if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
         & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) 
            == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                    * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                 ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) 
                                               * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                               ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                       ((IData)(1U) 
                                        + (7U & (((IData)(0x2aU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                 >> 5U)))] 
                                       << ((IData)(0x20U) 
                                           - (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                             | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                (7U & (((IData)(0x2aU) 
                                        * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                       >> 5U))] >> 
                                (0x1fU & ((IData)(0x2aU) 
                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                 : 0U)))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                       << 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, 
                          vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U]);
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                               << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] 
                                            >> 0xaU))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                       << 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, 
                          vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U]);
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                               << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                                           >> 0x14U))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                       << 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, 
                          vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U]);
    }
    if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
          >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] 
                               << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                                         >> 0x1eU))) 
                    == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                         ? (0xffU & (((0U == (0x1fU 
                                              & ((IData)(0x2aU) 
                                                 * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                               ((IData)(1U) 
                                                + (7U 
                                                   & (((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                      >> 5U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x2aU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                        (7U & (((IData)(0x2aU) 
                                                * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                               >> 5U))] 
                                        >> (0x1fU & 
                                            ((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                         : 0U)))) {
        VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) 
                                       >> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, 
                          vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]);
    }
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) 
           | ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
              & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) 
                 == ((0xa7U >= (0xffU & ((IData)(0x2aU) 
                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                      ? (0xffU & (((0U == (0x1fU & 
                                           ((IData)(0x2aU) 
                                            * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                    ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                            ((IData)(1U) 
                                             + (7U 
                                                & (((IData)(0x2aU) 
                                                    * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                   >> 5U)))] 
                                            << ((IData)(0x20U) 
                                                - (0x1fU 
                                                   & ((IData)(0x2aU) 
                                                      * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                  | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                     (7U & (((IData)(0x2aU) 
                                             * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                            >> 5U))] 
                                     >> (0x1fU & ((IData)(0x2aU) 
                                                  * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                      : 0U))));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) 
           | (0xfffffffeU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
                             & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                                            << 0x16U) 
                                           | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] 
                                              >> 0xaU))) 
                                 == ((0xa7U >= (0xffU 
                                                & ((IData)(0x2aU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                      ? (0xffU & ((
                                                   (0U 
                                                    == 
                                                    (0x1fU 
                                                     & ((IData)(0x2aU) 
                                                        * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                                    ? 0U
                                                    : 
                                                   (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                    ((IData)(1U) 
                                                     + 
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U)))] 
                                                    << 
                                                    ((IData)(0x20U) 
                                                     - 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                                  | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U))] 
                                                     >> 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                                      : 0U)) << 1U))));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) 
           | (0xfffffffcU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
                             & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                                            << 0xcU) 
                                           | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] 
                                              >> 0x14U))) 
                                 == ((0xa7U >= (0xffU 
                                                & ((IData)(0x2aU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                      ? (0xffU & ((
                                                   (0U 
                                                    == 
                                                    (0x1fU 
                                                     & ((IData)(0x2aU) 
                                                        * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                                    ? 0U
                                                    : 
                                                   (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                    ((IData)(1U) 
                                                     + 
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U)))] 
                                                    << 
                                                    ((IData)(0x20U) 
                                                     - 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                                  | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U))] 
                                                     >> 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                                      : 0U)) << 2U))));
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) 
           | (0xfffffff8U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) 
                             & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] 
                                            << 2U) 
                                           | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] 
                                              >> 0x1eU))) 
                                 == ((0xa7U >= (0xffU 
                                                & ((IData)(0x2aU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                      ? (0xffU & ((
                                                   (0U 
                                                    == 
                                                    (0x1fU 
                                                     & ((IData)(0x2aU) 
                                                        * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
                                                    ? 0U
                                                    : 
                                                   (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                    ((IData)(1U) 
                                                     + 
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U)))] 
                                                    << 
                                                    ((IData)(0x20U) 
                                                     - 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) 
                                                  | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
                                                     (7U 
                                                      & (((IData)(0x2aU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) 
                                                         >> 5U))] 
                                                     >> 
                                                     (0x1fU 
                                                      & ((IData)(0x2aU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
                                      : 0U)) << 3U))));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) 
                 >> (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)));
    vlTOPp->__Vtableidx4 = vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid;
    vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank 
        = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank
        [vlTOPp->__Vtableidx4];
    vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid 
        = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid
        [vlTOPp->__Vtableidx4];
    vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx4];
    vlTOPp->__Vtableidx2 = vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank 
        = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank
        [vlTOPp->__Vtableidx2];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid 
        = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid
        [vlTOPp->__Vtableidx2];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i 
        = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i
        [vlTOPp->__Vtableidx2];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           << 5U)) | (0xfffffffU & 
                                      ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                        << 0x19U) | 
                                       (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                        >> 7U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                           << 3U)) | (0xfffffffU & 
                                      ((0xfffffe0U 
                                        & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                                           << 5U)) 
                                       | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                          >> 0x1bU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] 
        = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                           << 5U)) | (0xfffffffU & 
                                      ((0x3ffffcU & 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                         >> 1U)) | 
                                       (3U & ((0xffffff8U 
                                               & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  << 3U)) 
                                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x1dU))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] 
        = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
                           << 7U)) | ((0xffffffc0U 
                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in) 
                                          << 6U)) | 
                                      (0x3fU & ((0x3fffe0U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                    << 5U)) 
                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                                   >> 0x1bU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x18U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           << 5U)) | (0xfffffffU & 
                                      ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                        << 0x19U) | 
                                       (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                        >> 7U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                           << 3U)) | (0xfffffffU & 
                                      ((0xfffffe0U 
                                        & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                                           << 5U)) 
                                       | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                          >> 0x1bU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] 
        = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                           << 5U)) | (0xfffffffU & 
                                      ((0x3ffffcU & 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                         >> 1U)) | 
                                       (3U & ((0xffffff8U 
                                               & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  << 3U)) 
                                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x1dU))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] 
        = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
                           << 7U)) | ((0xffffffc0U 
                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in) 
                                          << 6U)) | 
                                      (0x3fU & ((0x3fffe0U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                    << 5U)) 
                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                                   >> 0x1bU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x18U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           << 5U)) | (0xfffffffU & 
                                      ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                        << 0x19U) | 
                                       (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                        >> 7U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                           << 3U)) | (0xfffffffU & 
                                      ((0xfffffe0U 
                                        & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                                           << 5U)) 
                                       | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                          >> 0x1bU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] 
        = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                           << 5U)) | (0xfffffffU & 
                                      ((0x3ffffcU & 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                         >> 1U)) | 
                                       (3U & ((0xffffff8U 
                                               & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  << 3U)) 
                                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x1dU))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] 
        = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
                           << 7U)) | ((0xffffffc0U 
                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in) 
                                          << 6U)) | 
                                      (0x3fU & ((0x3fffe0U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                    << 5U)) 
                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                                   >> 0x1bU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) 
                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                    >> 0x18U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           << 5U)) | (0xfffffffU & 
                                      ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                        << 0x19U) | 
                                       (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                                        >> 7U))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
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                          (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] 
        = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                         << 5U)) | 
                          (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] 
                           >> 0x1bU))) | (0xf0000000U 
                                          & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                             << 5U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] 
        = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                           << 3U)) | (0xfffffffU & 
                                      ((0xfffffe0U 
                                        & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] 
                                           << 5U)) 
                                       | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] 
                                          >> 0x1bU))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] 
        = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                           << 5U)) | (0xfffffffU & 
                                      ((0x3ffffcU & 
                                        (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                         >> 1U)) | 
                                       (3U & ((0xffffff8U 
                                               & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  << 3U)) 
                                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x1dU))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] 
        = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
                           << 7U)) | ((0xffffffc0U 
                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in) 
                                          << 6U)) | 
                                      (0x3fU & ((0x3fffe0U 
                                                 & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] 
                                                    << 5U)) 
                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] 
                                                   >> 0x1bU)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) 
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    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual 
        = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) 
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    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
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            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) 
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    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e 
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    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match 
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    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual 
        = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) 
                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) 
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            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) 
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    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match 
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    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual 
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                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) 
               & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) 
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            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) 
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        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
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            [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
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    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match 
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                & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) 
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             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) 
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    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
            [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match 
        = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                        [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c
           [0U]);
    vlTOPp->core_rsp_data[0U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U];
    vlTOPp->core_rsp_data[1U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U];
    vlTOPp->core_rsp_data[2U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U];
    vlTOPp->core_rsp_data[3U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U];
    vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value 
        = (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) 
           | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) 
               ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original))));
    vlTOPp->snp_rsp_valid = vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid;
    vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)));
    vlTOPp->snp_rsp_tag = ((0x6fU >= (0x7fU & ((IData)(0x1cU) 
                                               * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))))
                            ? (0xfffffffU & (((0U == 
                                               (0x1fU 
                                                & ((IData)(0x1cU) 
                                                   * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))))
                                               ? 0U
                                               : (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[
                                                  ((IData)(1U) 
                                                   + 
                                                   (3U 
                                                    & (((IData)(0x1cU) 
                                                        * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) 
                                                       >> 5U)))] 
                                                  << 
                                                  ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(0x1cU) 
                                                       * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) 
                                             | (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[
                                                (3U 
                                                 & (((IData)(0x1cU) 
                                                     * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) 
                                                    >> 5U))] 
                                                >> 
                                                (0x1fU 
                                                 & ((IData)(0x1cU) 
                                                    * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))))))
                            : 0U);
    vlTOPp->dram_req_rw = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid;
    vlTOPp->dram_req_valid = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) 
                              | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = 0U;
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r) 
           | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)));
    vlTOPp->dram_req_byteen = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                ? (0xffffU & (IData)(
                                                     (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen 
                                                      >> 
                                                      (0x3fU 
                                                       & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                          << 4U)))))
                                : 0xffffU);
    vlTOPp->dram_req_data[0U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                  ? (((0U == (0x1fU 
                                              & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                 << 7U)))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                               ((IData)(1U) 
                                                + (0xcU 
                                                   & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                      << 2U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                       << 7U))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                        (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                 << 2U))] 
                                        >> (0x1fU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 7U))))
                                  : 0U);
    vlTOPp->dram_req_data[1U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                  ? (((0U == (0x1fU 
                                              & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                 << 7U)))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                               ((IData)(2U) 
                                                + (0xcU 
                                                   & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                      << 2U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                       << 7U))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                        ((IData)(1U) 
                                         + (0xcU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 2U)))] 
                                        >> (0x1fU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 7U))))
                                  : 0U);
    vlTOPp->dram_req_data[2U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                  ? (((0U == (0x1fU 
                                              & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                 << 7U)))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                               ((IData)(3U) 
                                                + (0xcU 
                                                   & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                      << 2U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                       << 7U))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                        ((IData)(2U) 
                                         + (0xcU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 2U)))] 
                                        >> (0x1fU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 7U))))
                                  : 0U);
    vlTOPp->dram_req_data[3U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                  ? (((0U == (0x1fU 
                                              & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                 << 7U)))
                                       ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                               ((IData)(4U) 
                                                + (0xcU 
                                                   & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                      << 2U)))] 
                                               << ((IData)(0x20U) 
                                                   - 
                                                   (0x1fU 
                                                    & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                                       << 7U))))) 
                                     | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[
                                        ((IData)(3U) 
                                         + (0xcU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 2U)))] 
                                        >> (0x1fU & 
                                            ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) 
                                             << 7U))))
                                  : 0U);
    vlTOPp->dram_req_addr = (0xfffffffU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)
                                            ? ((0x6fU 
                                                >= 
                                                (0x7fU 
                                                 & ((IData)(0x1cU) 
                                                    * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))))
                                                ? (
                                                   ((0U 
                                                     == 
                                                     (0x1fU 
                                                      & ((IData)(0x1cU) 
                                                         * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))))
                                                     ? 0U
                                                     : 
                                                    (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[
                                                     ((IData)(1U) 
                                                      + 
                                                      (3U 
                                                       & (((IData)(0x1cU) 
                                                           * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) 
                                                          >> 5U)))] 
                                                     << 
                                                     ((IData)(0x20U) 
                                                      - 
                                                      (0x1fU 
                                                       & ((IData)(0x1cU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))))) 
                                                   | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[
                                                      (3U 
                                                       & (((IData)(0x1cU) 
                                                           * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) 
                                                          >> 5U))] 
                                                      >> 
                                                      (0x1fU 
                                                       & ((IData)(0x1cU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))))
                                                : 0U)
                                            : ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)
                                                ? (
                                                   (0x6fU 
                                                    >= 
                                                    (0x7fU 
                                                     & ((IData)(0x1cU) 
                                                        * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))
                                                    ? 
                                                   (((0U 
                                                      == 
                                                      (0x1fU 
                                                       & ((IData)(0x1cU) 
                                                          * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))
                                                      ? 0U
                                                      : 
                                                     (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[
                                                      ((IData)(1U) 
                                                       + 
                                                       (3U 
                                                        & (((IData)(0x1cU) 
                                                            * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) 
                                                           >> 5U)))] 
                                                      << 
                                                      ((IData)(0x20U) 
                                                       - 
                                                       (0x1fU 
                                                        & ((IData)(0x1cU) 
                                                           * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) 
                                                    | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[
                                                       (3U 
                                                        & (((IData)(0x1cU) 
                                                            * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) 
                                                           >> 5U))] 
                                                       >> 
                                                       (0x1fU 
                                                        & ((IData)(0x1cU) 
                                                           * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))
                                                    : 0U)
                                                : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
                                 & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) 
                                & ((0x3ffffffU & ((
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   << 7U) 
                                                  | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                     >> 0x19U))) 
                                   == (0x3ffffffU & 
                                       vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) 
                 | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
                     & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                     [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                              << 7U) 
                                             | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                >> 0x19U))) 
                              == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                              [0U]))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
           & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
           & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
              >> 0x1aU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
                                 & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) 
                                & ((0x3ffffffU & ((
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   << 7U) 
                                                  | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                     >> 0x19U))) 
                                   == (0x3ffffffU & 
                                       vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) 
                 | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
                     & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                     [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                              << 7U) 
                                             | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                >> 0x19U))) 
                              == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                              [0U]))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
           & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
           & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
              >> 0x1aU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
                                 & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) 
                                & ((0x3ffffffU & ((
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   << 7U) 
                                                  | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                     >> 0x19U))) 
                                   == (0x3ffffffU & 
                                       vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) 
                 | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
                     & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                     [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                              << 7U) 
                                             | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                >> 0x19U))) 
                              == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                              [0U]))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
           & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
           & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
              >> 0x1aU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
                                 & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) 
                                & ((0x3ffffffU & ((
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   << 7U) 
                                                  | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                     >> 0x19U))) 
                                   == (0x3ffffffU & 
                                       vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) 
                 | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
                     & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                     [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                              << 7U) 
                                             | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                >> 0x19U))) 
                              == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                              [0U]))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
           & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
           & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
           & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
              >> 0x1aU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
            [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                      [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                               [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss 
        = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
              [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
                      [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                                [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                                          [0U])) | 
           ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
               [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
                       [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                       [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
            [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                      [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                               [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss 
        = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
              [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1
                      [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                                [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                                          [0U])) | 
           ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
               [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1
                       [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                       [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
            [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                      [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                               [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss 
        = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
              [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1
                      [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                                [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                                          [0U])) | 
           ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
               [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1
                       [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                       [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
            [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                      [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                               [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss 
        = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
              [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
                      [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
                                [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                                          [0U])) | 
           ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
               [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
                       [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                       [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing 
        = ((((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)));
    vlTOPp->dram_req_tag = vlTOPp->dram_req_addr;
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) 
                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing 
        = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
             & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                   >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) 
                                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) 
                                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) 
           | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) 
                << 3U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                           << 3U) | (0x1f8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                >> 0x17U) 
                                               & ((~ 
                                                   (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                    >> 0x1bU)) 
                                                  << 3U))))) 
              & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) 
                      | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) 
                     | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall))) 
                 << 3U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) 
             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e 
        = (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
             [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1
                     [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
                               | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) 
                                  & (((0x3ffffffU & 
                                       ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                         << 7U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                   >> 0x19U))) 
                                      == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                                      [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  >> 0x14U)))))) 
           | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1
               [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) 
                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing 
        = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
             & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                   >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) 
                                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) 
                                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) 
           | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) 
                << 2U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                           << 2U) | (0xfcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                               >> 0x18U) 
                                              & ((~ 
                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x1bU)) 
                                                 << 2U))))) 
              & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) 
                      | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) 
                     | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall))) 
                 << 2U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) 
             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e 
        = (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
             [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1
                     [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
                               | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) 
                                  & (((0x3ffffffU & 
                                       ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                         << 7U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                   >> 0x19U))) 
                                      == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1
                                      [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  >> 0x14U)))))) 
           | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1
               [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) 
                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing 
        = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
             & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                   >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) 
                                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) 
                                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) 
           | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) 
                << 1U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                           << 1U) | (0x7eU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                               >> 0x19U) 
                                              & ((~ 
                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                   >> 0x1bU)) 
                                                 << 1U))))) 
              & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) 
                      | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) 
                     | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall))) 
                 << 1U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) 
             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e 
        = (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
             [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1
                     [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
                               | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) 
                                  & (((0x3ffffffU & 
                                       ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                         << 7U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                   >> 0x19U))) 
                                      == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1
                                      [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  >> 0x14U)))))) 
           | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1
               [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) 
                 | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) 
                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) 
                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing 
        = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) 
              & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
             & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] 
                   >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) 
                                   | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) 
                                  | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) 
               & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) 
                  | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                      >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                      >> 0x1bU))))) 
              & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) 
                     | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) 
                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe 
        = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) 
             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) 
           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e 
        = (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
             [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1
                     [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) 
                               | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) 
                                  & (((0x3ffffffU & 
                                       ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                         << 7U) | (
                                                   vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                   >> 0x19U))) 
                                      == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
                                      [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                                  >> 0x14U)))))) 
           | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1
               [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1
           [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1
           [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1
           [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1
           [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1
           [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1
           [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1
           [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1
           [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1
           [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1
           [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1
           [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1
           [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1
           [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1
           [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1
           [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1
           [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1
           [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending 
        = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
               [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) 
            & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
               [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1
            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending 
        = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1
               [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) 
            & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
               [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1
            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending 
        = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1
               [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) 
            & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
               [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U] 
        = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U] 
        = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U] 
        = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U];
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U] 
        = ((0xffff0000U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid) 
                           << 0x10U)) | vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]);
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing 
        = (((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq 
        = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                   >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
                                >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
            [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending 
        = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
               [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
               [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) 
            & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c
               [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1
               [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head 
        = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible));
    __Vtemp401[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                ? (
                                                   (VL_ULL(0x1ffffffffff80) 
                                                    & (((QData)((IData)(
                                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                        [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                        << 0x3eU) 
                                                       | (((QData)((IData)(
                                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                           [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                           << 0x1eU) 
                                                          | (VL_ULL(0x3fffffffffffff80) 
                                                             & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                >> 2U))))) 
                                                   | (QData)((IData)(
                                                                     (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                       << 6U) 
                                                                      | ((0x3cU 
                                                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                              << 0x1eU) 
                                                                             | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                         | (3U 
                                                                            & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                               | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                    ? 
                                                   ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                     << 7U) 
                                                    | (QData)((IData)(
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                        << 6U) 
                                                                       | ((0x3cU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                               >> 
                                                                               (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                              << 2U)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                    : 
                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                     ? 
                                                    ((QData)((IData)(
                                                                     (0xfffffffU 
                                                                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                     << 7U)
                                                     : VL_ULL(0))))) 
                                      << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual));
    __Vtemp401[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                       ? ((VL_ULL(0x1ffffffffff80) 
                                           & (((QData)((IData)(
                                                               vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                               [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                               << 0x3eU) 
                                              | (((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                  [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                  << 0x1eU) 
                                                 | (VL_ULL(0x3fffffffffffff80) 
                                                    & ((QData)((IData)(
                                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                       >> 2U))))) 
                                          | (QData)((IData)(
                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                              << 6U) 
                                                             | ((0x3cU 
                                                                 & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                     [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                     << 0x1eU) 
                                                                    | (0x3ffffffcU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 2U)))) 
                                                                | (3U 
                                                                   & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                       << 0xdU) 
                                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                         [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                         >> 0x13U))))))))
                                       : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                           ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                               << 7U) 
                                              | (QData)((IData)(
                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                  << 6U) 
                                                                 | ((0x3cU 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                         >> 
                                                                         (0xfU 
                                                                          & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                             << 2U))) 
                                                                        << 2U)) 
                                                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                           : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                               ? ((QData)((IData)(
                                                                  (0xfffffffU 
                                                                   & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                  << 7U)
                                               : VL_ULL(0))))) 
                             >> 0x1fU)) | (0xfffffffeU 
                                           & ((IData)(
                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                         ? 
                                                        ((VL_ULL(0x1ffffffffff80) 
                                                          & (((QData)((IData)(
                                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                              << 0x3eU) 
                                                             | (((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                                 << 0x1eU) 
                                                                | (VL_ULL(0x3fffffffffffff80) 
                                                                   & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                      >> 2U))))) 
                                                         | (QData)((IData)(
                                                                           (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                             << 6U) 
                                                                            | ((0x3cU 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                               | (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                         : 
                                                        ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                          ? 
                                                         ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                           << 7U) 
                                                          | (QData)((IData)(
                                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                              << 6U) 
                                                                             | ((0x3cU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                                >> 
                                                                                (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                                << 2U)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                          : 
                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                           ? 
                                                          ((QData)((IData)(
                                                                           (0xfffffffU 
                                                                            & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                           << 7U)
                                                           : VL_ULL(0)))) 
                                                       >> 0x20U)) 
                                              << 1U)));
    __Vtemp402[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)(
                                                                ((0x80000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 1U))
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 1U
                                                                        : 0U)) 
                                                                     << 0x1fU)) 
                                                                 | ((0x40000000U 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                          ? 
                                                                         (1U 
                                                                          & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                          : 
                                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                           ? 
                                                                          (1U 
                                                                           & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                           : 0U)) 
                                                                        << 0x1eU)) 
                                                                    | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                          ? 1U
                                                                          : 
                                                                         (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                           ? 1U
                                                                           : 
                                                                          (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                            & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                            ? 1U
                                                                            : 0U))) 
                                                                        << 0x1dU) 
                                                                       | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) 
                                                                              | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) 
                                                                            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) 
                                                                           << 0x1cU) 
                                                                          | ((0xffffffcU 
                                                                              & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                             | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                << 0x20U) 
                                               | (QData)((IData)(
                                                                 ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                   ? 
                                                                  ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                    [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                    << 0xbU) 
                                                                   | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                      [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                      >> 0x15U))
                                                                   : 
                                                                  ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                    ? 
                                                                   (((0U 
                                                                      == 
                                                                      (0x1fU 
                                                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                          << 5U)))
                                                                      ? 0U
                                                                      : 
                                                                     (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                      ((IData)(1U) 
                                                                       + 
                                                                       (3U 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                      << 
                                                                      ((IData)(0x20U) 
                                                                       - 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                           << 5U))))) 
                                                                    | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                       (3U 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                       >> 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                           << 5U))))
                                                                    : 0U)))))) 
                                      << 0x12U)) | 
                      __Vtemp401[5U]);
    __Vtemp402[6U] = ((0x3ffffU & ((IData)((((QData)((IData)(
                                                             ((0x80000000U 
                                                               & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
                                                                        & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U)))))) 
                                   >> 0xeU)) | (0xfffc0000U 
                                                & ((IData)(
                                                           ((((QData)((IData)(
                                                                              ((0x80000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 1U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 0U)) 
                                                                                << 0x1fU)) 
                                                                               | ((0x40000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (1U 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                                 : 0U)) 
                                                                                << 0x1eU)) 
                                                                                | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                                 ? 1U
                                                                                 : 0U))) 
                                                                                << 0x1dU) 
                                                                                | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) 
                                                                                << 0x1cU) 
                                                                                | ((0xffffffcU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                                | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                              << 0x20U) 
                                                             | (QData)((IData)(
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xbU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x15U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U)))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))
                                                                                 : 0U))))) 
                                                            >> 0x20U)) 
                                                   << 0x12U)));
    __Vtemp402[7U] = (0x3ffffU & ((IData)(((((QData)((IData)(
                                                             ((0x80000000U 
                                                               & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
                                                                        & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U))))) 
                                           >> 0x20U)) 
                                  >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]
            : 0x39U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] 
        = __Vtemp401[4U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] 
        = __Vtemp402[5U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] 
        = __Vtemp402[6U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] 
        = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                           << 0x12U)) | __Vtemp402[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) 
           | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) 
                 & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
                    [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                              [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
               [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head 
        = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible));
    __Vtemp415[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                ? (
                                                   (VL_ULL(0x1ffffffffff80) 
                                                    & (((QData)((IData)(
                                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                        [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                        << 0x3eU) 
                                                       | (((QData)((IData)(
                                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                           [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                           << 0x1eU) 
                                                          | (VL_ULL(0x3fffffffffffff80) 
                                                             & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                >> 2U))))) 
                                                   | (QData)((IData)(
                                                                     (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                       << 6U) 
                                                                      | ((0x3cU 
                                                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                              << 0x1eU) 
                                                                             | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                         | (3U 
                                                                            & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                               | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                    ? 
                                                   ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                     << 7U) 
                                                    | (QData)((IData)(
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                        << 6U) 
                                                                       | ((0x3cU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                               >> 
                                                                               (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                              << 2U)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                    : 
                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                     ? 
                                                    ((QData)((IData)(
                                                                     (0xfffffffU 
                                                                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                     << 7U)
                                                     : VL_ULL(0))))) 
                                      << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual));
    __Vtemp415[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                       ? ((VL_ULL(0x1ffffffffff80) 
                                           & (((QData)((IData)(
                                                               vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                               [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                               << 0x3eU) 
                                              | (((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                  [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                  << 0x1eU) 
                                                 | (VL_ULL(0x3fffffffffffff80) 
                                                    & ((QData)((IData)(
                                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                       >> 2U))))) 
                                          | (QData)((IData)(
                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                              << 6U) 
                                                             | ((0x3cU 
                                                                 & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                     [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                     << 0x1eU) 
                                                                    | (0x3ffffffcU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 2U)))) 
                                                                | (3U 
                                                                   & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                       << 0xdU) 
                                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                         [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                         >> 0x13U))))))))
                                       : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                           ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                               << 7U) 
                                              | (QData)((IData)(
                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                  << 6U) 
                                                                 | ((0x3cU 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                         >> 
                                                                         (0xfU 
                                                                          & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                             << 2U))) 
                                                                        << 2U)) 
                                                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                           : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                               ? ((QData)((IData)(
                                                                  (0xfffffffU 
                                                                   & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                  << 7U)
                                               : VL_ULL(0))))) 
                             >> 0x1fU)) | (0xfffffffeU 
                                           & ((IData)(
                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                         ? 
                                                        ((VL_ULL(0x1ffffffffff80) 
                                                          & (((QData)((IData)(
                                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                              << 0x3eU) 
                                                             | (((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                                 << 0x1eU) 
                                                                | (VL_ULL(0x3fffffffffffff80) 
                                                                   & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                      >> 2U))))) 
                                                         | (QData)((IData)(
                                                                           (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                             << 6U) 
                                                                            | ((0x3cU 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                               | (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                         : 
                                                        ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                          ? 
                                                         ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                           << 7U) 
                                                          | (QData)((IData)(
                                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                              << 6U) 
                                                                             | ((0x3cU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                                >> 
                                                                                (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                                << 2U)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                          : 
                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                           ? 
                                                          ((QData)((IData)(
                                                                           (0xfffffffU 
                                                                            & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                           << 7U)
                                                           : VL_ULL(0)))) 
                                                       >> 0x20U)) 
                                              << 1U)));
    __Vtemp416[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)(
                                                                ((0x80000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 1U))
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 1U
                                                                        : 0U)) 
                                                                     << 0x1fU)) 
                                                                 | ((0x40000000U 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                          ? 
                                                                         (1U 
                                                                          & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                          : 
                                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                           ? 
                                                                          (1U 
                                                                           & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                           : 0U)) 
                                                                        << 0x1eU)) 
                                                                    | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                          ? 1U
                                                                          : 
                                                                         (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                           ? 1U
                                                                           : 
                                                                          (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                            & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                            ? 1U
                                                                            : 0U))) 
                                                                        << 0x1dU) 
                                                                       | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) 
                                                                              | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) 
                                                                            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) 
                                                                           << 0x1cU) 
                                                                          | ((0xffffffcU 
                                                                              & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                             | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
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                                               | (QData)((IData)(
                                                                 ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                   ? 
                                                                  ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                    [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                    << 0xbU) 
                                                                   | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                      [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                      >> 0x15U))
                                                                   : 
                                                                  ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                    ? 
                                                                   (((0U 
                                                                      == 
                                                                      (0x1fU 
                                                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                          << 5U)))
                                                                      ? 0U
                                                                      : 
                                                                     (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                      ((IData)(1U) 
                                                                       + 
                                                                       (3U 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                      << 
                                                                      ((IData)(0x20U) 
                                                                       - 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                           << 5U))))) 
                                                                    | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                       (3U 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                       >> 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                           << 5U))))
                                                                    : 0U)))))) 
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                                                             ((0x80000000U 
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                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
                                                                        & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
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                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
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                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
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                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U)))))) 
                                   >> 0xeU)) | (0xfffc0000U 
                                                & ((IData)(
                                                           ((((QData)((IData)(
                                                                              ((0x80000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 1U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 0U)) 
                                                                                << 0x1fU)) 
                                                                               | ((0x40000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (1U 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                                 : 0U)) 
                                                                                << 0x1eU)) 
                                                                                | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                                 ? 1U
                                                                                 : 0U))) 
                                                                                << 0x1dU) 
                                                                                | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) 
                                                                                << 0x1cU) 
                                                                                | ((0xffffffcU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                                | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                              << 0x20U) 
                                                             | (QData)((IData)(
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xbU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x15U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U)))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))
                                                                                 : 0U))))) 
                                                            >> 0x20U)) 
                                                   << 0x12U)));
    __Vtemp416[7U] = (0x3ffffU & ((IData)(((((QData)((IData)(
                                                             ((0x80000000U 
                                                               & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
                                                                        & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U))))) 
                                           >> 0x20U)) 
                                  >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]
            : 0x39U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] 
        = __Vtemp415[4U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] 
        = __Vtemp416[5U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] 
        = __Vtemp416[6U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] 
        = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                           << 0x12U)) | __Vtemp416[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) 
           | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) 
                 & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1
                    [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
                              [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1
               [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head 
        = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible));
    __Vtemp429[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                ? (
                                                   (VL_ULL(0x1ffffffffff80) 
                                                    & (((QData)((IData)(
                                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                        [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                        << 0x3eU) 
                                                       | (((QData)((IData)(
                                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                           [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                           << 0x1eU) 
                                                          | (VL_ULL(0x3fffffffffffff80) 
                                                             & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                >> 2U))))) 
                                                   | (QData)((IData)(
                                                                     (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                       << 6U) 
                                                                      | ((0x3cU 
                                                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                              << 0x1eU) 
                                                                             | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                         | (3U 
                                                                            & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                               | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                    ? 
                                                   ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                     << 7U) 
                                                    | (QData)((IData)(
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                        << 6U) 
                                                                       | ((0x3cU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                               >> 
                                                                               (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                              << 2U)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                    : 
                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                     ? 
                                                    ((QData)((IData)(
                                                                     (0xfffffffU 
                                                                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                     << 7U)
                                                     : VL_ULL(0))))) 
                                      << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual));
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                                       ? ((VL_ULL(0x1ffffffffff80) 
                                           & (((QData)((IData)(
                                                               vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                               [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                               << 0x3eU) 
                                              | (((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                  [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                  << 0x1eU) 
                                                 | (VL_ULL(0x3fffffffffffff80) 
                                                    & ((QData)((IData)(
                                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                       >> 2U))))) 
                                          | (QData)((IData)(
                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                              << 6U) 
                                                             | ((0x3cU 
                                                                 & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                     [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                     << 0x1eU) 
                                                                    | (0x3ffffffcU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 2U)))) 
                                                                | (3U 
                                                                   & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                       << 0xdU) 
                                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                         [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                         >> 0x13U))))))))
                                       : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                           ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                               << 7U) 
                                              | (QData)((IData)(
                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                  << 6U) 
                                                                 | ((0x3cU 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                         >> 
                                                                         (0xfU 
                                                                          & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                             << 2U))) 
                                                                        << 2U)) 
                                                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                           : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                               ? ((QData)((IData)(
                                                                  (0xfffffffU 
                                                                   & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                  << 7U)
                                               : VL_ULL(0))))) 
                             >> 0x1fU)) | (0xfffffffeU 
                                           & ((IData)(
                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                         ? 
                                                        ((VL_ULL(0x1ffffffffff80) 
                                                          & (((QData)((IData)(
                                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                              << 0x3eU) 
                                                             | (((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                                 << 0x1eU) 
                                                                | (VL_ULL(0x3fffffffffffff80) 
                                                                   & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                      >> 2U))))) 
                                                         | (QData)((IData)(
                                                                           (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                             << 6U) 
                                                                            | ((0x3cU 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                               | (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                         : 
                                                        ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                          ? 
                                                         ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                           << 7U) 
                                                          | (QData)((IData)(
                                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                              << 6U) 
                                                                             | ((0x3cU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                                >> 
                                                                                (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                                << 2U)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                          : 
                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                           ? 
                                                          ((QData)((IData)(
                                                                           (0xfffffffU 
                                                                            & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                           << 7U)
                                                           : VL_ULL(0)))) 
                                                       >> 0x20U)) 
                                              << 1U)));
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                                                                ((0x80000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 1U))
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 1U
                                                                        : 0U)) 
                                                                     << 0x1fU)) 
                                                                 | ((0x40000000U 
                                                                     & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                          ? 
                                                                         (1U 
                                                                          & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                          : 
                                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                           ? 
                                                                          (1U 
                                                                           & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                           : 0U)) 
                                                                        << 0x1eU)) 
                                                                    | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                          ? 1U
                                                                          : 
                                                                         (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                           ? 1U
                                                                           : 
                                                                          (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                            & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                            ? 1U
                                                                            : 0U))) 
                                                                        << 0x1dU) 
                                                                       | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) 
                                                                              | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) 
                                                                            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) 
                                                                           << 0x1cU) 
                                                                          | ((0xffffffcU 
                                                                              & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                             | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                << 0x20U) 
                                               | (QData)((IData)(
                                                                 ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                   ? 
                                                                  ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                    [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                    << 0xbU) 
                                                                   | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                      [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                      >> 0x15U))
                                                                   : 
                                                                  ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                    ? 
                                                                   (((0U 
                                                                      == 
                                                                      (0x1fU 
                                                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                          << 5U)))
                                                                      ? 0U
                                                                      : 
                                                                     (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                      ((IData)(1U) 
                                                                       + 
                                                                       (3U 
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                                                                      << 
                                                                      ((IData)(0x20U) 
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                                                                       (0x1fU 
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                                                                       >> 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
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                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
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                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) 
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                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) 
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                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
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                                                                                (0x3ffffffU 
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                                                                                (0x1fU 
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                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
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                                                                                (0xfU 
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                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
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                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
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                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
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                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
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                                                                                (0x3ffffffU 
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                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
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                                                                                >> 0x1dU)))
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                                                                                (3U 
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                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
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                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
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                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
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                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
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                                                                       << 5U)))
                                                                   ? 0U
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                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
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                                                                   << 
                                                                   ((IData)(0x20U) 
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                                                                    (0x1fU 
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                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
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                                                                    >> 
                                                                    (0x1fU 
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                                                                        << 5U))))
                                                                 : 0U)))))) 
                                   >> 0xeU)) | (0xfffc0000U 
                                                & ((IData)(
                                                           ((((QData)((IData)(
                                                                              ((0x80000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 1U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 0U)) 
                                                                                << 0x1fU)) 
                                                                               | ((0x40000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
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                                                                                (1U 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                                 : 0U)) 
                                                                                << 0x1eU)) 
                                                                                | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                                 ? 1U
                                                                                 : 0U))) 
                                                                                << 0x1dU) 
                                                                                | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) 
                                                                                << 0x1cU) 
                                                                                | ((0xffffffcU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                                | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                              << 0x20U) 
                                                             | (QData)((IData)(
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xbU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x15U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U)))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))
                                                                                 : 0U))))) 
                                                            >> 0x20U)) 
                                                   << 0x12U)));
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                                                             ((0x80000000U 
                                                               & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
                                                                        & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U))))) 
                                           >> 0x20U)) 
                                  >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]
            : 0x39U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] 
        = __Vtemp429[4U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] 
        = __Vtemp430[5U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] 
        = __Vtemp430[6U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] 
        = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                           << 0x12U)) | __Vtemp430[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) 
           | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) 
                 & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1
                    [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
                              [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1
               [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head 
        = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) 
            & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop) 
           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible));
    __Vtemp443[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                ? (
                                                   (VL_ULL(0x1ffffffffff80) 
                                                    & (((QData)((IData)(
                                                                        vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                        [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                        << 0x3eU) 
                                                       | (((QData)((IData)(
                                                                           vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                           [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                           << 0x1eU) 
                                                          | (VL_ULL(0x3fffffffffffff80) 
                                                             & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                >> 2U))))) 
                                                   | (QData)((IData)(
                                                                     (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                                       << 6U) 
                                                                      | ((0x3cU 
                                                                          & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                              << 0x1eU) 
                                                                             | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                         | (3U 
                                                                            & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                               | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                    ? 
                                                   ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
                                                     << 7U) 
                                                    | (QData)((IData)(
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                        << 6U) 
                                                                       | ((0x3cU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) 
                                                                               >> 
                                                                               (0xfU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 2U))) 
                                                                              << 2U)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                    : 
                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                     ? 
                                                    ((QData)((IData)(
                                                                     (0xfffffffU 
                                                                      & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) 
                                                     << 7U)
                                                     : VL_ULL(0))))) 
                                      << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual));
    __Vtemp443[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                       ? ((VL_ULL(0x1ffffffffff80) 
                                           & (((QData)((IData)(
                                                               vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                               [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                               << 0x3eU) 
                                              | (((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                  [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                  << 0x1eU) 
                                                 | (VL_ULL(0x3fffffffffffff80) 
                                                    & ((QData)((IData)(
                                                                       vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                       >> 2U))))) 
                                          | (QData)((IData)(
                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) 
                                                              << 6U) 
                                                             | ((0x3cU 
                                                                 & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                     [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                     << 0x1eU) 
                                                                    | (0x3ffffffcU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                          [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                          >> 2U)))) 
                                                                | (3U 
                                                                   & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                       << 0xdU) 
                                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                         [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                         >> 0x13U))))))))
                                       : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                           ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
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                                              | (QData)((IData)(
                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) 
                                                                  << 6U) 
                                                                 | ((0x3cU 
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                                                                         >> 
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                                                                        << 2U)) 
                                                                    | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
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                                               ? ((QData)((IData)(
                                                                  (0xfffffffU 
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                                                  << 7U)
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                             >> 0x1fU)) | (0xfffffffeU 
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                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                         ? 
                                                        ((VL_ULL(0x1ffffffffff80) 
                                                          & (((QData)((IData)(
                                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                              [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) 
                                                              << 0x3eU) 
                                                             | (((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) 
                                                                 << 0x1eU) 
                                                                | (VL_ULL(0x3fffffffffffff80) 
                                                                   & ((QData)((IData)(
                                                                                vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) 
                                                                      >> 2U))))) 
                                                         | (QData)((IData)(
                                                                           (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) 
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                                                                            | ((0x3cU 
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                                                                                << 0x1eU) 
                                                                                | (0x3ffffffcU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))) 
                                                                               | (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xdU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x13U))))))))
                                                         : 
                                                        ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                          ? 
                                                         ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag 
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                                                          | (QData)((IData)(
                                                                            (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) 
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                                                                             | ((0x3cU 
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                                                                                >> 
                                                                                (0xfU 
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                                                                                << 2U)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))))))
                                                          : 
                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                           ? 
                                                          ((QData)((IData)(
                                                                           (0xfffffffU 
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                                                                      (1U 
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                                                                          >> 1U))
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 1U
                                                                        : 0U)) 
                                                                     << 0x1fU)) 
                                                                 | ((0x40000000U 
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                                                                         (1U 
                                                                          & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                          : 
                                                                         ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
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                                                                          (1U 
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                                                                        << 0x1eU)) 
                                                                    | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                          ? 1U
                                                                          : 
                                                                         (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                           & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                           ? 1U
                                                                           : 
                                                                          (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                            & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                            ? 1U
                                                                            : 0U))) 
                                                                        << 0x1dU) 
                                                                       | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) 
                                                                              | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                             | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) 
                                                                            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) 
                                                                           << 0x1cU) 
                                                                          | ((0xffffffcU 
                                                                              & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
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                                                                                (0x3ffffffU 
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                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
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                                                                                 ? 0U
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                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
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                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                             | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                << 0x20U) 
                                               | (QData)((IData)(
                                                                 ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                   ? 
                                                                  ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                    [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                    << 0xbU) 
                                                                   | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                      [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                      >> 0x15U))
                                                                   : 
                                                                  ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                    ? 
                                                                   (((0U 
                                                                      == 
                                                                      (0x1fU 
                                                                       & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                          << 5U)))
                                                                      ? 0U
                                                                      : 
                                                                     (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
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                                                                       + 
                                                                       (3U 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                      << 
                                                                      ((IData)(0x20U) 
                                                                       - 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                           << 5U))))) 
                                                                    | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                       (3U 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                       >> 
                                                                       (0x1fU 
                                                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                           << 5U))))
                                                                    : 0U)))))) 
                                      << 0x12U)) | 
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                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
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                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
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                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U)))))) 
                                   >> 0xeU)) | (0xfffc0000U 
                                                & ((IData)(
                                                           ((((QData)((IData)(
                                                                              ((0x80000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 1U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 0U)) 
                                                                                << 0x1fU)) 
                                                                               | ((0x40000000U 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (1U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (1U 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                                 : 0U)) 
                                                                                << 0x1eU)) 
                                                                                | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                                 ? 1U
                                                                                 : 
                                                                                (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                                 ? 1U
                                                                                 : 0U))) 
                                                                                << 0x1dU) 
                                                                                | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) 
                                                                                | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) 
                                                                                << 0x1cU) 
                                                                                | ((0xffffffcU 
                                                                                & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                                << 2U)) 
                                                                                | (3U 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                                              << 0x20U) 
                                                             | (QData)((IData)(
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                                << 0xbU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                >> 0x15U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U)))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                                (3U 
                                                                                & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                                << 5U))))
                                                                                 : 0U))))) 
                                                            >> 0x20U)) 
                                                   << 0x12U)));
    __Vtemp444[7U] = (0x3ffffU & ((IData)(((((QData)((IData)(
                                                             ((0x80000000U 
                                                               & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                    ? 
                                                                   (1U 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                       >> 1U))
                                                                    : 
                                                                   ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                     ? 1U
                                                                     : 0U)) 
                                                                  << 0x1fU)) 
                                                              | ((0x40000000U 
                                                                  & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                       ? 
                                                                      (1U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                       [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])
                                                                       : 
                                                                      ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                        ? 
                                                                       (1U 
                                                                        & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1cU)))
                                                                        : 0U)) 
                                                                     << 0x1eU)) 
                                                                 | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                       ? 1U
                                                                       : 
                                                                      (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                                                                        & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0))
                                                                        ? 1U
                                                                        : 
                                                                       (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) 
                                                                         & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0))
                                                                         ? 1U
                                                                         : 0U))) 
                                                                     << 0x1dU) 
                                                                    | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) 
                                                                           | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) 
                                                                          | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) 
                                                                         | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) 
                                                                        << 0x1cU) 
                                                                       | ((0xffffffcU 
                                                                           & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
                                                                                ? 
                                                                               (0x3ffffffU 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])
                                                                                : 
                                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                ((0x19fU 
                                                                                >= 
                                                                                (0x1ffU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))
                                                                                 ? 0U
                                                                                 : 
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U)))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[
                                                                                (0xfU 
                                                                                & (((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) 
                                                                                >> 5U))] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & ((IData)(0x1aU) 
                                                                                * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))))))
                                                                                 : 0U)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 
                                                                                >> 4U))
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)
                                                                                 ? 
                                                                                (0x3ffffffU 
                                                                                & (IData)(
                                                                                (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out 
                                                                                >> 0x1dU)))
                                                                                 : 0U)))) 
                                                                              << 2U)) 
                                                                          | (3U 
                                                                             & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                                 ? 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0)
                                                                                 : 
                                                                                ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                                 ? 
                                                                                (3U 
                                                                                & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                                << 0x1eU) 
                                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                                [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] 
                                                                                >> 2U)))
                                                                                 : 0U)))))))))) 
                                             << 0x20U) 
                                            | (QData)((IData)(
                                                              ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)
                                                                ? 
                                                               ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                 [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] 
                                                                 << 0xbU) 
                                                                | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table
                                                                   [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] 
                                                                   >> 0x15U))
                                                                : 
                                                               ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)
                                                                 ? 
                                                                (((0U 
                                                                   == 
                                                                   (0x1fU 
                                                                    & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                       << 5U)))
                                                                   ? 0U
                                                                   : 
                                                                  (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                   ((IData)(1U) 
                                                                    + 
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] 
                                                                   << 
                                                                   ((IData)(0x20U) 
                                                                    - 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))) 
                                                                 | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[
                                                                    (3U 
                                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] 
                                                                    >> 
                                                                    (0x1fU 
                                                                     & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) 
                                                                        << 5U))))
                                                                 : 0U))))) 
                                           >> 0x20U)) 
                                  >> 0xeU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]
            : 0x39U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)
            ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]
            : 0U);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] 
        = __Vtemp443[4U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] 
        = __Vtemp444[5U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] 
        = __Vtemp444[6U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] 
        = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) 
                           << 0x12U)) | __Vtemp444[7U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e 
        = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) 
            | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) 
           | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) 
                 & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
                    [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
                              [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
               [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))));
    __Vtemp446[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
        [0U][0U];
    __Vtemp446[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
        [0U][1U];
    __Vtemp446[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
        [0U][2U];
    __Vtemp446[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
        [0U][3U];
    __Vtemp453[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
                                    [0U][3U] >> 9U)) 
                      | (0xff800000U & ((IData)((((QData)((IData)(
                                                                  vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
                                                                  [0U])) 
                                                  << 0x20U) 
                                                 | (QData)((IData)(
                                                                   (((0U 
                                                                      == 
                                                                      (0x1fU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                          [0U] 
                                                                          << 5U)))
                                                                      ? 0U
                                                                      : 
                                                                     (__Vtemp446[
                                                                      ((IData)(1U) 
                                                                       + 
                                                                       (3U 
                                                                        & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                        [0U]))] 
                                                                      << 
                                                                      ((IData)(0x20U) 
                                                                       - 
                                                                       (0x1fU 
                                                                        & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                           [0U] 
                                                                           << 5U))))) 
                                                                    | (__Vtemp446[
                                                                       (3U 
                                                                        & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                        [0U])] 
                                                                       >> 
                                                                       (0x1fU 
                                                                        & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                           [0U] 
                                                                           << 5U)))))))) 
                                        << 0x17U)));
    __Vtemp453[7U] = ((0x7fffffU & ((IData)((((QData)((IData)(
                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
                                                              [0U])) 
                                              << 0x20U) 
                                             | (QData)((IData)(
                                                               (((0U 
                                                                  == 
                                                                  (0x1fU 
                                                                   & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                      [0U] 
                                                                      << 5U)))
                                                                  ? 0U
                                                                  : 
                                                                 (__Vtemp446[
                                                                  ((IData)(1U) 
                                                                   + 
                                                                   (3U 
                                                                    & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                    [0U]))] 
                                                                  << 
                                                                  ((IData)(0x20U) 
                                                                   - 
                                                                   (0x1fU 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                       [0U] 
                                                                       << 5U))))) 
                                                                | (__Vtemp446[
                                                                   (3U 
                                                                    & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                    [0U])] 
                                                                   >> 
                                                                   (0x1fU 
                                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                       [0U] 
                                                                       << 5U)))))))) 
                                    >> 9U)) | (0xff800000U 
                                               & ((IData)(
                                                          ((((QData)((IData)(
                                                                             vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
                                                                             [0U])) 
                                                             << 0x20U) 
                                                            | (QData)((IData)(
                                                                              (((0U 
                                                                                == 
                                                                                (0x1fU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                                [0U] 
                                                                                << 5U)))
                                                                                 ? 0U
                                                                                 : 
                                                                                (__Vtemp446[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                                [0U]))] 
                                                                                << 
                                                                                ((IData)(0x20U) 
                                                                                - 
                                                                                (0x1fU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                                [0U] 
                                                                                << 5U))))) 
                                                                               | (__Vtemp446[
                                                                                (3U 
                                                                                & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                                [0U])] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                                [0U] 
                                                                                << 5U))))))) 
                                                           >> 0x20U)) 
                                                  << 0x17U)));
    __Vtemp454[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                      [0U] << 0x17U)) 
                      | (0x7fffffU & ((IData)(((((QData)((IData)(
                                                                 vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1
                                                                 [0U])) 
                                                 << 0x20U) 
                                                | (QData)((IData)(
                                                                  (((0U 
                                                                     == 
                                                                     (0x1fU 
                                                                      & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                         [0U] 
                                                                         << 5U)))
                                                                     ? 0U
                                                                     : 
                                                                    (__Vtemp446[
                                                                     ((IData)(1U) 
                                                                      + 
                                                                      (3U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                       [0U]))] 
                                                                     << 
                                                                     ((IData)(0x20U) 
                                                                      - 
                                                                      (0x1fU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                          [0U] 
                                                                          << 5U))))) 
                                                                   | (__Vtemp446[
                                                                      (3U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                       [0U])] 
                                                                      >> 
                                                                      (0x1fU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                                                                          [0U] 
                                                                          << 5U))))))) 
                                               >> 0x20U)) 
                                      >> 9U)));
    __Vtemp456[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) 
                                       | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) 
                                            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
                                               [0U])) 
                                           & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                                              [0U])) 
                                          & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
                                          [0U])) << 0x19U)) 
                      | (0x1ffffffU & ((0x1000000U 
                                        & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) 
                                           << 0x18U)) 
                                       | ((0x1800000U 
                                           & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1
                                              [0U] 
                                              << 0x17U)) 
                                          | ((0x1c00000U 
                                              & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1
                                                 [0U] 
                                                 << 0x16U)) 
                                             | ((0x1e00000U 
                                                 & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) 
                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)) 
                                                    << 0x15U)) 
                                                | ((0x1f00000U 
                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                                                       [0U] 
                                                       << 0x14U)) 
                                                   | ((0x1f80000U 
                                                       & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1
                                                           [0U] 
                                                           & (~ 
                                                              vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
                                                              [0U])) 
                                                          << 0x13U)) 
                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1
                                                         [0U] 
                                                         >> 7U)))))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] 
        = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                  [0U]);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] 
        = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c
                           [0U] << 0x11U)) | (IData)(
                                                     (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                                                      [0U] 
                                                      >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] 
        = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
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                                                                     (__Vtemp459[
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                                                                 (__Vtemp459[
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                                                                                (__Vtemp459[
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                                                                                << 
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                                                                                >> 
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                                                                    (__Vtemp459[
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                                                                     << 
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                                                                      (0x1fU 
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                                                                      >> 
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                                                                     (__Vtemp472[
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                                                                 (__Vtemp472[
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                                                                                (__Vtemp472[
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                                                                    (__Vtemp472[
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                                                                     << 
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                                                                      (0x1fU 
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                                                                      (0x1fU 
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                                                        | (0x1ffffU 
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                                                 | (QData)((IData)(
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                                                                     (__Vtemp485[
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                                                                       + 
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                                                                      << 
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                                             | (QData)((IData)(
                                                               (((0U 
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                                                                      << 5U)))
                                                                  ? 0U
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                                                                 (__Vtemp485[
                                                                  ((IData)(1U) 
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                                                                  << 
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                                                                | (__Vtemp485[
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                                                                   >> 
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                                    >> 9U)) | (0xff800000U 
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                                                            | (QData)((IData)(
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                                                                                << 5U)))
                                                                                 ? 0U
                                                                                 : 
                                                                                (__Vtemp485[
                                                                                ((IData)(1U) 
                                                                                + 
                                                                                (3U 
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                                                                                << 
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                                                                                - 
                                                                                (0x1fU 
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                                                                                << 5U))))) 
                                                                               | (__Vtemp485[
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                                                                                [0U])] 
                                                                                >> 
                                                                                (0x1fU 
                                                                                & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                                                                                [0U] 
                                                                                << 5U))))))) 
                                                           >> 0x20U)) 
                                                  << 0x17U)));
    __Vtemp493[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
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                      | (0x7fffffU & ((IData)(((((QData)((IData)(
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                                                 << 0x20U) 
                                                | (QData)((IData)(
                                                                  (((0U 
                                                                     == 
                                                                     (0x1fU 
                                                                      & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
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                                                                     ? 0U
                                                                     : 
                                                                    (__Vtemp485[
                                                                     ((IData)(1U) 
                                                                      + 
                                                                      (3U 
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                                                                       [0U]))] 
                                                                     << 
                                                                     ((IData)(0x20U) 
                                                                      - 
                                                                      (0x1fU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                                                                          [0U] 
                                                                          << 5U))))) 
                                                                   | (__Vtemp485[
                                                                      (3U 
                                                                       & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
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                                                                      >> 
                                                                      (0x1fU 
                                                                       & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                                                                          [0U] 
                                                                          << 5U))))))) 
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                                                     & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)) 
                                                    << 0x15U)) 
                                                | ((0x1f00000U 
                                                    & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
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                                                   | ((0x1f80000U 
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                                                           & (~ 
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                                                      | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
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                                                     (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1
                                                      [0U] 
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    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] 
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                                                      << 3U)) 
                                                  | ((0xfffffffcU 
                                                      & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) 
                                                         << 2U)) 
                                                     | ((0xfffffffeU 
                                                         & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e) 
                                                            << 1U)) 
                                                        | (0x1ffffU 
                                                           & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c
                                                              [0U] 
                                                              >> 0xfU))))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] 
        = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
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    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] 
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                                                << 0x17U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] 
        = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
                         [0U][2U] >> 9U)) | (0xff800000U 
                                             & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c
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                                                << 0x17U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] 
        = __Vtemp492[6U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] 
        = __Vtemp492[7U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] 
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    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] 
        = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
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                            & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] 
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                                              | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] 
                                                 >> 0x19U))) 
                               == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1
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           ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1
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        = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1
                        [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1
               [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c
              [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e))) 
            & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1
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    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
               ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                           [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                          ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
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                          : 0U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
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    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
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    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
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                           [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                          ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1
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           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
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                                              [0U] 
                                              >> 2U)))
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           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
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                                              >> 2U)))
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                                              >> 2U)))
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                                              [0U] 
                                              >> 2U)))
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                ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
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        = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
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                ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
               ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                           [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                          ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1
                                             [0U] >> 2U)))
                          : 0U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 4U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 8U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we 
        = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) 
           | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)
                ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1
                            [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write))
                           ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1
                                              [0U] 
                                              >> 2U)))
                           : 0U)) << 0xcU));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1
            [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)))
            ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1
            [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)))
            ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1
            [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)))
            ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable 
        = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1
            [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)))
            ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)));
}

VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_combo__TOP__5\n"); );
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in 
        = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr 
                                           >> 2U)))) 
            << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) 
                                          << 0x1cU) 
                                         | vlTOPp->snp_req_tag))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in 
        = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr 
                                           >> 2U)))) 
            << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) 
                                          << 0x1cU) 
                                         | vlTOPp->snp_req_tag))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in 
        = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr 
                                           >> 2U)))) 
            << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) 
                                          << 0x1cU) 
                                         | vlTOPp->snp_req_tag))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in 
        = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr 
                                           >> 2U)))) 
            << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) 
                                          << 0x1cU) 
                                         | vlTOPp->snp_req_tag))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] 
        = vlTOPp->dram_rsp_data[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] 
        = vlTOPp->dram_rsp_data[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] 
        = vlTOPp->dram_rsp_data[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] 
        = vlTOPp->dram_rsp_data[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] 
        = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] 
        = vlTOPp->dram_rsp_data[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] 
        = vlTOPp->dram_rsp_data[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] 
        = vlTOPp->dram_rsp_data[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] 
        = vlTOPp->dram_rsp_data[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] 
        = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] 
        = vlTOPp->dram_rsp_data[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] 
        = vlTOPp->dram_rsp_data[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] 
        = vlTOPp->dram_rsp_data[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] 
        = vlTOPp->dram_rsp_data[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] 
        = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] 
        = vlTOPp->dram_rsp_data[0U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] 
        = vlTOPp->dram_rsp_data[1U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] 
        = vlTOPp->dram_rsp_data[2U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] 
        = vlTOPp->dram_rsp_data[3U];
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] 
        = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing 
        = (((IData)(vlTOPp->snp_req_valid) & (3U == 
                                              (3U & vlTOPp->snp_req_addr))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing 
        = (((IData)(vlTOPp->snp_req_valid) & (2U == 
                                              (3U & vlTOPp->snp_req_addr))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing 
        = (((IData)(vlTOPp->snp_req_valid) & (1U == 
                                              (3U & vlTOPp->snp_req_addr))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing 
        = (((IData)(vlTOPp->snp_req_valid) & (0U == 
                                              (3U & vlTOPp->snp_req_addr))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing 
        = (((IData)(vlTOPp->dram_rsp_valid) & (3U == 
                                               (3U 
                                                & vlTOPp->dram_rsp_tag))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing 
        = (((IData)(vlTOPp->dram_rsp_valid) & (2U == 
                                               (3U 
                                                & vlTOPp->dram_rsp_tag))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing 
        = (((IData)(vlTOPp->dram_rsp_valid) & (1U == 
                                               (3U 
                                                & vlTOPp->dram_rsp_tag))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing 
        = (((IData)(vlTOPp->dram_rsp_valid) & (0U == 
                                               (3U 
                                                & vlTOPp->dram_rsp_tag))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->snp_req_ready = (1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) 
                                   >> (3U & vlTOPp->snp_req_addr)));
    vlTOPp->core_req_ready = (0xfU == ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready) 
                                       | (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)));
    vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready 
        = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual) 
           & VL_NEGATE_I((IData)((IData)(vlTOPp->core_rsp_ready))));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = 
        ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) 
         | ((IData)(vlTOPp->snp_rsp_ready) & (0U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = 
        ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) 
         | (((IData)(vlTOPp->snp_rsp_ready) & (1U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) 
            << 1U));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = 
        ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) 
         | (((IData)(vlTOPp->snp_rsp_ready) & (2U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) 
            << 2U));
    vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = 
        ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) 
         | (((IData)(vlTOPp->snp_rsp_ready) & (3U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) 
            << 3U));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop 
        = (((~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)) 
            & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)) 
           & (IData)(vlTOPp->dram_req_ready));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready 
        = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) 
           | ((IData)(vlTOPp->dram_req_ready) & (0U 
                                                 == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready 
        = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) 
           | (((IData)(vlTOPp->dram_req_ready) & (1U 
                                                  == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) 
              << 1U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready 
        = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) 
           | (((IData)(vlTOPp->dram_req_ready) & (2U 
                                                  == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) 
              << 2U));
    vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready 
        = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) 
           | (((IData)(vlTOPp->dram_req_ready) & (3U 
                                                  == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) 
              << 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid 
        = (0xfU & ((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) 
                   & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid 
        = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) 
                    >> 4U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid 
        = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) 
                    >> 8U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid 
        = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) 
                    >> 0xcU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)) 
                 & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) 
                     >> 1U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) 
                     >> 2U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading 
        = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) 
                  & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) 
                     >> 3U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid) 
           & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) 
              >> 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) 
              >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) 
              >> 3U));
    vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading 
        = ((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) 
             & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) 
            & (~ ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] 
                                             >> 0x10U))))) 
                  | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid) 
           & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) 
              >> 1U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) 
              >> 2U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire 
        = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) 
           & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) 
              >> 3U));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing 
        = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] 
        = (IData)(vlTOPp->core_req_tag);
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] 
        = ((0xfffffc00U & (vlTOPp->core_req_data[0U] 
                           << 0xaU)) | (IData)((vlTOPp->core_req_tag 
                                                >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] 
        = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] 
        = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] 
        = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] 
        = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] 
                           << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] 
                                                  >> 0x16U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] 
        = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid) 
                           << 0x16U)) | ((0xfffc0000U 
                                          & ((IData)(vlTOPp->core_req_rw) 
                                             << 0x12U)) 
                                         | ((0xfffffffcU 
                                             & ((IData)(vlTOPp->core_req_byteen) 
                                                << 2U)) 
                                            | (0x3ffU 
                                               & (vlTOPp->core_req_addr[3U] 
                                                  >> 0x16U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing 
        = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] 
        = (IData)(vlTOPp->core_req_tag);
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] 
        = ((0xfffffc00U & (vlTOPp->core_req_data[0U] 
                           << 0xaU)) | (IData)((vlTOPp->core_req_tag 
                                                >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] 
        = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] 
        = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] 
        = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] 
        = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] 
                           << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] 
                                                  >> 0x16U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] 
        = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid) 
                           << 0x16U)) | ((0xfffc0000U 
                                          & ((IData)(vlTOPp->core_req_rw) 
                                             << 0x12U)) 
                                         | ((0xfffffffcU 
                                             & ((IData)(vlTOPp->core_req_byteen) 
                                                << 2U)) 
                                            | (0x3ffU 
                                               & (vlTOPp->core_req_addr[3U] 
                                                  >> 0x16U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing 
        = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] 
        = (IData)(vlTOPp->core_req_tag);
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] 
        = ((0xfffffc00U & (vlTOPp->core_req_data[0U] 
                           << 0xaU)) | (IData)((vlTOPp->core_req_tag 
                                                >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] 
        = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] 
        = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] 
        = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] 
        = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] 
                           << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] 
                                                  >> 0x16U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] 
        = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid) 
                           << 0x16U)) | ((0xfffc0000U 
                                          & ((IData)(vlTOPp->core_req_rw) 
                                             << 0x12U)) 
                                         | ((0xfffffffcU 
                                             & ((IData)(vlTOPp->core_req_byteen) 
                                                << 2U)) 
                                            | (0x3ffU 
                                               & (vlTOPp->core_req_addr[3U] 
                                                  >> 0x16U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing 
        = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) 
             & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
            & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] 
        = (IData)(vlTOPp->core_req_tag);
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] 
        = ((0xfffffc00U & (vlTOPp->core_req_data[0U] 
                           << 0xaU)) | (IData)((vlTOPp->core_req_tag 
                                                >> 0x20U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] 
        = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] 
        = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] 
        = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_data[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] 
        = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] 
                           << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] 
                                                  >> 0x16U)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[1U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[2U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] 
        = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) 
           | (0xfffffc00U & (vlTOPp->core_req_addr[3U] 
                             << 0xaU)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] 
        = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid) 
                           << 0x16U)) | ((0xfffc0000U 
                                          & ((IData)(vlTOPp->core_req_rw) 
                                             << 0x12U)) 
                                         | ((0xfffffffcU 
                                             & ((IData)(vlTOPp->core_req_byteen) 
                                                << 2U)) 
                                            | (0x3ffU 
                                               & (vlTOPp->core_req_addr[3U] 
                                                  >> 0x16U)))));
    vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading 
        = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                             >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) 
             | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                  >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                               >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) 
            | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                 >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                           >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading 
        = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                             >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) 
             | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                  >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                               >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) 
            | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                 >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                           >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading 
        = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                             >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) 
             | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                  >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                               >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) 
            | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                 >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                           >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
    vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading 
        = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                             >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) 
             | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                  >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                               >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) 
            | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                 >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] 
                           >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) 
           & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)));
}

void VVX_cache::_eval(VVX_cache__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_eval\n"); );
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->_combo__TOP__2(vlSymsp);
    vlTOPp->__Vm_traceActivity = (2U | vlTOPp->__Vm_traceActivity);
    if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
        vlTOPp->_sequent__TOP__4(vlSymsp);
        vlTOPp->__Vm_traceActivity = (4U | vlTOPp->__Vm_traceActivity);
    }
    vlTOPp->_combo__TOP__5(vlSymsp);
    // Final
    vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}

void VVX_cache::_eval_initial(VVX_cache__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_eval_initial\n"); );
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->_initial__TOP__1(vlSymsp);
    vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}

void VVX_cache::final() {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::final\n"); );
    // Variables
    VVX_cache__Syms* __restrict vlSymsp = this->__VlSymsp;
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}

void VVX_cache::_eval_settle(VVX_cache__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_eval_settle\n"); );
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    vlTOPp->_settle__TOP__3(vlSymsp);
    vlTOPp->__Vm_traceActivity = (1U | vlTOPp->__Vm_traceActivity);
}

VL_INLINE_OPT QData VVX_cache::_change_request(VVX_cache__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_change_request\n"); );
    VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    // Change detection
    QData __req = false;  // Logically a bool
    return __req;
}

#ifdef VL_DEBUG
void VVX_cache::_eval_debug_assertions() {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_eval_debug_assertions\n"); );
    // Body
    if (VL_UNLIKELY((clk & 0xfeU))) {
        Verilated::overWidthError("clk");}
    if (VL_UNLIKELY((reset & 0xfeU))) {
        Verilated::overWidthError("reset");}
    if (VL_UNLIKELY((core_req_valid & 0xf0U))) {
        Verilated::overWidthError("core_req_valid");}
    if (VL_UNLIKELY((core_req_rw & 0xf0U))) {
        Verilated::overWidthError("core_req_rw");}
    if (VL_UNLIKELY((core_rsp_ready & 0xfeU))) {
        Verilated::overWidthError("core_rsp_ready");}
    if (VL_UNLIKELY((dram_req_ready & 0xfeU))) {
        Verilated::overWidthError("dram_req_ready");}
    if (VL_UNLIKELY((dram_rsp_valid & 0xfeU))) {
        Verilated::overWidthError("dram_rsp_valid");}
    if (VL_UNLIKELY((dram_rsp_tag & 0xf0000000U))) {
        Verilated::overWidthError("dram_rsp_tag");}
    if (VL_UNLIKELY((snp_req_valid & 0xfeU))) {
        Verilated::overWidthError("snp_req_valid");}
    if (VL_UNLIKELY((snp_req_addr & 0xf0000000U))) {
        Verilated::overWidthError("snp_req_addr");}
    if (VL_UNLIKELY((snp_req_invalidate & 0xfeU))) {
        Verilated::overWidthError("snp_req_invalidate");}
    if (VL_UNLIKELY((snp_req_tag & 0xf0000000U))) {
        Verilated::overWidthError("snp_req_tag");}
    if (VL_UNLIKELY((snp_rsp_ready & 0xfeU))) {
        Verilated::overWidthError("snp_rsp_ready");}
    if (VL_UNLIKELY((snp_fwdout_ready & 0xfcU))) {
        Verilated::overWidthError("snp_fwdout_ready");}
    if (VL_UNLIKELY((snp_fwdin_valid & 0xfcU))) {
        Verilated::overWidthError("snp_fwdin_valid");}
}
#endif  // VL_DEBUG

void VVX_cache::_ctor_var_reset() {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_cache::_ctor_var_reset\n"); );
    // Body
    clk = VL_RAND_RESET_I(1);
    reset = VL_RAND_RESET_I(1);
    core_req_valid = VL_RAND_RESET_I(4);
    core_req_rw = VL_RAND_RESET_I(4);
    core_req_byteen = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(120, core_req_addr);
    VL_RAND_RESET_W(128, core_req_data);
    core_req_tag = VL_RAND_RESET_Q(42);
    core_req_ready = VL_RAND_RESET_I(1);
    core_rsp_valid = VL_RAND_RESET_I(4);
    VL_RAND_RESET_W(128, core_rsp_data);
    core_rsp_tag = VL_RAND_RESET_Q(42);
    core_rsp_ready = VL_RAND_RESET_I(1);
    dram_req_valid = VL_RAND_RESET_I(1);
    dram_req_rw = VL_RAND_RESET_I(1);
    dram_req_byteen = VL_RAND_RESET_I(16);
    dram_req_addr = VL_RAND_RESET_I(28);
    VL_RAND_RESET_W(128, dram_req_data);
    dram_req_tag = VL_RAND_RESET_I(28);
    dram_req_ready = VL_RAND_RESET_I(1);
    dram_rsp_valid = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(128, dram_rsp_data);
    dram_rsp_tag = VL_RAND_RESET_I(28);
    dram_rsp_ready = VL_RAND_RESET_I(1);
    snp_req_valid = VL_RAND_RESET_I(1);
    snp_req_addr = VL_RAND_RESET_I(28);
    snp_req_invalidate = VL_RAND_RESET_I(1);
    snp_req_tag = VL_RAND_RESET_I(28);
    snp_req_ready = VL_RAND_RESET_I(1);
    snp_rsp_valid = VL_RAND_RESET_I(1);
    snp_rsp_tag = VL_RAND_RESET_I(28);
    snp_rsp_ready = VL_RAND_RESET_I(1);
    snp_fwdout_valid = VL_RAND_RESET_I(2);
    snp_fwdout_addr = VL_RAND_RESET_Q(56);
    snp_fwdout_invalidate = VL_RAND_RESET_I(2);
    snp_fwdout_tag = VL_RAND_RESET_I(2);
    snp_fwdout_ready = VL_RAND_RESET_I(2);
    snp_fwdin_valid = VL_RAND_RESET_I(2);
    snp_fwdin_tag = VL_RAND_RESET_I(2);
    snp_fwdin_ready = VL_RAND_RESET_I(2);
    VX_cache__DOT__per_bank_core_req_ready = VL_RAND_RESET_I(4);
    VX_cache__DOT__per_bank_core_rsp_valid = VL_RAND_RESET_I(4);
    VX_cache__DOT__per_bank_core_rsp_tid = VL_RAND_RESET_I(8);
    VL_RAND_RESET_W(128, VX_cache__DOT__per_bank_core_rsp_data);
    VL_RAND_RESET_W(168, VX_cache__DOT__per_bank_core_rsp_tag);
    VX_cache__DOT__per_bank_core_rsp_ready = VL_RAND_RESET_I(4);
    VX_cache__DOT__per_bank_dram_fill_req_valid = VL_RAND_RESET_I(4);
    VL_RAND_RESET_W(112, VX_cache__DOT__per_bank_dram_fill_req_addr);
    VX_cache__DOT__per_bank_dram_fill_rsp_ready = VL_RAND_RESET_I(4);
    VX_cache__DOT__per_bank_dram_wb_req_ready = VL_RAND_RESET_I(4);
    VX_cache__DOT__per_bank_dram_wb_req_valid = VL_RAND_RESET_I(4);
    VX_cache__DOT__per_bank_dram_wb_req_byteen = VL_RAND_RESET_Q(64);
    VL_RAND_RESET_W(112, VX_cache__DOT__per_bank_dram_wb_req_addr);
    VL_RAND_RESET_W(512, VX_cache__DOT__per_bank_dram_wb_req_data);
    VX_cache__DOT__per_bank_snp_req_ready = VL_RAND_RESET_I(4);
    VX_cache__DOT__per_bank_snp_rsp_valid = VL_RAND_RESET_I(4);
    VL_RAND_RESET_W(112, VX_cache__DOT__per_bank_snp_rsp_tag);
    VX_cache__DOT__per_bank_snp_rsp_ready = VL_RAND_RESET_I(4);
    VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(128, VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = VL_RAND_RESET_I(4);
    VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank = VL_RAND_RESET_I(2);
    VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid = VL_RAND_RESET_I(2);
    VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr = VL_RAND_RESET_I(28);
    VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r = VL_RAND_RESET_I(28);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid = VL_RAND_RESET_I(4);
    VL_RAND_RESET_W(112, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid = VL_RAND_RESET_I(4);
    VL_RAND_RESET_W(112, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr);
    VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out);
    VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index = VL_RAND_RESET_I(2);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index = VL_RAND_RESET_I(2);
    VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = VL_RAND_RESET_I(4);
    VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use = VL_RAND_RESET_I(4);
    VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value = VL_RAND_RESET_I(4);
    VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill = VL_RAND_RESET_I(1);
    VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original = VL_RAND_RESET_I(4);
    VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank = VL_RAND_RESET_I(2);
    VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid = VL_RAND_RESET_I(1);
    VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[__Vi0]);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55);
    }}
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr);
    VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]);
    }}
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]);
    }}
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20);
    }}
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16);
    }}
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32);
    VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value);
    VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]);
    }}
    VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[__Vi0]);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55);
    }}
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr);
    VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]);
    }}
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]);
    }}
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20);
    }}
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16);
    }}
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32);
    VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value);
    VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]);
    }}
    VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[__Vi0]);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55);
    }}
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr);
    VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]);
    }}
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]);
    }}
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20);
    }}
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16);
    }}
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32);
    VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value);
    VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]);
    }}
    VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[__Vi0]);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1);
    }}
    VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55);
    }}
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr);
    VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32);
    VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value);
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20);
    }}
    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]);
    }}
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16);
    VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]);
    }}
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20);
    }}
    { int __Vi0=0; for (; __Vi0<64; ++__Vi0) {
            VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16);
    }}
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32);
    VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value);
    VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value);
    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
            VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]);
    }}
    VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1);
    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
            VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]);
    }}
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r);
    VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1);
    VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1);
    __Vtableidx1 = 0;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[0] = 0U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[1] = 0U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[2] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[3] = 0U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[4] = 2U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[5] = 0U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[6] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[7] = 0U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[8] = 3U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[9] = 0U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[10] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[11] = 0U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[12] = 2U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[13] = 0U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[14] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[15] = 0U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[0] = 0U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[1] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[2] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[3] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[4] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[5] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[6] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[7] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[8] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[9] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[10] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[11] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[12] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[13] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[14] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[15] = 1U;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx2 = 0;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[0] = 0U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[1] = 0U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[2] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[3] = 0U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[4] = 2U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[5] = 0U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[6] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[7] = 0U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[8] = 3U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[9] = 0U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[10] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[11] = 0U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[12] = 2U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[13] = 0U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[14] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[15] = 0U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[0] = 0U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[1] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[2] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[3] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[4] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[5] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[6] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[7] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[8] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[9] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[10] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[11] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[12] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[13] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[14] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[15] = 1U;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx3 = 0;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[0] = 0U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[1] = 0U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[2] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[3] = 0U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[4] = 2U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[5] = 0U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[6] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[7] = 0U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[8] = 3U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[9] = 0U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[10] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[11] = 0U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[12] = 2U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[13] = 0U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[14] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[15] = 0U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[0] = 0U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[1] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[2] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[3] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[4] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[5] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[6] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[7] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[8] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[9] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[10] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[11] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[12] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[13] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[14] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[15] = 1U;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx4 = 0;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[0] = 0U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[1] = 0U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[2] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[3] = 0U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[4] = 2U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[5] = 0U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[6] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[7] = 0U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[8] = 3U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[9] = 0U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[10] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[11] = 0U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[12] = 2U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[13] = 0U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[14] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[15] = 0U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[0] = 0U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[1] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[2] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[3] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[4] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[5] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[6] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[7] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[8] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[9] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[10] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[11] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[12] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[13] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[14] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[15] = 1U;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx5 = 0;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx6 = 0;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx7 = 0;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vtableidx8 = 0;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU;
    __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU;
    __Vm_traceActivity = 0;
}