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  • bbb2373919 Intrinsics: tests for TMC+Control Divergence felsabbagh3 2019-11-01 21:53:37 -04:00
  • 2b9f6f3d0b Fixed eviction_wb Savan Roshan 2019-11-01 00:39:02 -04:00
  • 46b09028d0 Added runtime (kernel 2.0) felsabbagh3 2019-10-30 23:40:01 -04:00
  • 06e5f6df1d Init num cycles felsabbagh3 2019-10-30 15:18:52 -04:00
  • 7863175233 Set associative bank working felsabbagh3 2019-10-30 14:57:20 -04:00
  • 3b49b82c46 GPR ASIC Working felsabbagh3 2019-10-29 23:20:16 -04:00
  • 3caae2b88e Merge branch 'master' of https://github.gatech.edu/casl/Vortex felsabbagh3 2019-10-29 14:28:41 -04:00
  • 4aa04e76e6 Simulate debug felsabbagh3 2019-10-29 14:28:20 -04:00
  • 3609742707 Finished synthesis at 1GHz, cell count increases to 1870k Lingjun Zhu 2019-10-29 11:33:23 -04:00
  • 3c6f0b5d15 Included the SDC and DDC files Lingjun Zhu 2019-10-28 17:24:19 -04:00
  • fa5b476874 Added the synthesis netlist Lingjun Zhu 2019-10-28 17:11:15 -04:00
  • 0d8a7be5c6 Finished synthesis with optimization Lingjun Zhu 2019-10-28 17:10:30 -04:00
  • b6558714ca Finished synthesis with all memory but no optimization Lingjun Zhu 2019-10-28 16:18:11 -04:00
  • 0b30b3a35f Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data Lingjun Zhu 2019-10-28 15:06:23 -04:00
  • 50d567d70c Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation Lingjun Zhu 2019-10-28 14:49:55 -04:00
  • 557c987bb0 Updated files list felsabbagh3 2019-10-28 14:29:07 -04:00
  • 7af6575b97 SYN=1 felsabbagh3 2019-10-28 13:57:01 -04:00
  • 28ee1d3c36 Sucess Synthesis - Finding db felsabbagh3 2019-10-28 13:52:49 -04:00
  • a8d063e9ad Synthesis Cleanup 1 felsabbagh3 2019-10-28 13:43:12 -04:00
  • 88eab9e746 Removed dependancy on felsabbagh3 2019-10-27 22:30:32 -04:00
  • 8013708a5b Added fsyn for my synthesis felsabbagh3 2019-10-27 22:16:57 -04:00
  • 1b7f28273b Removed -O3 from makefile felsabbagh3 2019-10-27 20:34:32 -04:00
  • 0ee74bc566 migrated 100% to modelsim felsabbagh3 2019-10-27 20:08:44 -04:00
  • 715982cca7 Modelsim Working + Simulating + dumping - Some bugs felsabbagh3 2019-10-27 03:36:02 -04:00
  • 372c81d90c Generate VCD with ModelSim felsabbagh3 2019-10-26 19:35:21 -04:00
  • 6fda88b68f Modelsim Makefile compile + simulate - DPI felsabbagh3 2019-10-26 19:01:49 -04:00
  • ad46194d1b fixed width felsabbagh3 2019-10-26 00:39:27 -04:00
  • 1181af1df2 Modelsim basic sim felsabbagh3 2019-10-26 00:34:57 -04:00
  • 9110e8367e modelsim Elsabbagh 2019-10-25 23:41:34 -04:00
  • 667dbfbbe8 Trying icarus felsabbagh3 2019-10-25 22:54:02 -04:00
  • 820007ae80 NUM_REQ felsabbagh3 2019-10-25 13:46:31 -04:00
  • c85c01e082 Parametized cache felsabbagh3 2019-10-25 13:36:06 -04:00
  • 89d0390965 CACHE FINALLY WORKING felsabbagh3 2019-10-25 04:01:23 -04:00
  • 01efe02e8b CACHE WORKING just needs lb/sb felsabbagh3 2019-10-25 03:03:09 -04:00
  • 1e648c5819 FIxed first circular issue felsabbagh3 2019-10-24 10:38:04 -04:00
  • de8de00f6e Finished cache not tested felsabbagh3 2019-10-23 19:07:26 -04:00
  • 6340ffcc2a new cache states felsabbagh3 2019-10-23 15:07:14 -04:00
  • b4d921f49a set_top_level tcl felsabbagh3 2019-10-23 11:56:32 -04:00
  • 1645a04b1d Fixed SM + added def SYN felsabbagh3 2019-10-22 15:56:30 -04:00
  • 3cb5820ecd Merge branch 'master' of https://github.gatech.edu/casl/Vortex felsabbagh3 2019-10-22 13:19:00 -04:00
  • f68942c92a Added cache+shared memory search path felsabbagh3 2019-10-22 13:18:49 -04:00
  • c43b3800d8 added report power and save ddc to synthesis script Shim 2019-10-22 11:27:13 -04:00
  • 9d8273afe4 Finished Cache Integration felsabbagh3 2019-10-22 06:02:08 -04:00
  • b7af8c3f34 Integrated Shared Memory felsabbagh3 2019-10-22 05:03:47 -04:00
  • 1bfafca896 Cleanup before integration felsabbagh3 2019-10-22 03:03:17 -04:00
  • b3f464dd89 Barriers impl + tested felsabbagh3 2019-10-22 01:47:39 -04:00
  • 31d3d51392 WSPAWN imp + tested felsabbagh3 2019-10-21 23:35:53 -04:00
  • c21e400f9f Readded IPDOM stack + SPLIT/Join tested felsabbagh3 2019-10-21 21:26:21 -04:00
  • b6375e76de Readded IPDOM stack + SPLIT/Join tested felsabbagh3 2019-10-21 21:24:49 -04:00
  • eeb0a321a8 Finished synthesis with no optimization, cell count increasts to 100k Lingjun Zhu 2019-10-21 17:53:51 -04:00
  • e2cd8102eb Uncommented the necessary line about write_bit_mask on VX_gpr.v again, try synthesizing Lingjun Zhu 2019-10-21 17:09:51 -04:00
  • 0672389edc fix felsabbagh3 2019-10-21 12:16:17 -04:00
  • ce49e2f223 proper init warp scheduelr felsabbagh3 2019-10-21 12:13:34 -04:00
  • 8050419511 added begin felsabbagh3 2019-10-21 12:06:10 -04:00
  • 85004899bd added reset to ws felsabbagh3 2019-10-21 12:03:07 -04:00
  • 99586279d9 always fix stack felsabbagh3 2019-10-21 11:49:10 -04:00
  • 292c792339 generic stack reset felsabbagh3 2019-10-21 11:45:51 -04:00
  • 4bfdbb5188 reset posedge felsabbagh3 2019-10-21 11:34:12 -04:00
  • fd876144f5 .tcl mod felsabbagh3 2019-10-21 11:27:01 -04:00
  • 49b139d512 fix felsabbagh3 2019-10-21 11:24:45 -04:00
  • 121a985d12 Reset to Generic Register felsabbagh3 2019-10-21 11:21:13 -04:00
  • bab1852a99 Added Split/Join - not tested felsabbagh3 2019-10-21 03:03:15 -04:00
  • 84f5ccb484 Added CSR TID/WID reads felsabbagh3 2019-10-21 02:10:05 -04:00
  • 405926f66f Generated memory blocks for data cache (data), data cache (tag), shared memory Lingjun Zhu 2019-10-20 14:52:28 -04:00
  • 797801ebae CENA/CENB Modifications + Still not working felsabbagh3 2019-10-19 14:52:57 -04:00
  • 93531715bb Created a testbench and simulated the read/write of the register file Lingjun Zhu 2019-10-18 22:55:34 -04:00
  • 4cae140ac1 Mem technology compiling but still reading all zeros felsabbagh3 2019-10-18 16:45:42 -04:00
  • f7d826593f TMC working and tested felsabbagh3 2019-10-18 16:09:06 -04:00
  • f7b55427b4 Added ISA2 infrastructure with bugs felsabbagh3 2019-10-18 05:21:32 -04:00
  • 629ed3f8f9 Before ISA2.0 felsabbagh3 2019-10-18 04:15:34 -04:00
  • 559c64cb36 Cleanup felsabbagh3 2019-10-18 02:20:38 -04:00
  • 505bbc20c8 Removed FWD felsabbagh3 2019-10-18 02:01:39 -04:00
  • 6b729fd2ea minor felsabbagh3 2019-10-18 01:46:38 -04:00
  • ccbb2acab5 LSU+EXU minor felsabbagh3 2019-10-17 22:38:09 -04:00
  • 6779d0fade Instruction Multiplex LSU/EXU 1 cycle DONE felsabbagh3 2019-10-17 22:29:21 -04:00
  • 84d321a517 Create the memory blocks with CLN28HPM Lingjun Zhu 2019-10-17 15:38:48 -04:00
  • d164ebfbc6 Added log file of synthesis, too many registers are removed Lingjun Zhu 2019-10-17 14:25:54 -04:00
  • a4d6ada16d Fixed the issues of memory during synthesis Lingjun Zhu 2019-10-17 14:18:52 -04:00
  • 6cfb44396e Merge branch 'master' of https://github.gatech.edu/casl/Vortex Shim 2019-10-17 14:01:00 -04:00
  • 78e4067013 added log file Shim 2019-10-17 14:00:22 -04:00
  • 62db9ae691 minor felsabbagh3 2019-10-17 12:04:06 -04:00
  • 0bea82a2c3 added tcl file Shim 2019-10-17 11:55:18 -04:00
  • 9bf186fc77 minor felsabbagh3 2019-10-17 11:51:11 -04:00
  • e8a43fa7a9 minor felsabbagh3 2019-10-17 11:44:19 -04:00
  • 10fbb53c38 minor felsabbagh3 2019-10-17 11:29:40 -04:00
  • 33e20a2d80 minor felsabbagh3 2019-10-17 11:25:29 -04:00
  • b08297eafb minor felsabbagh3 2019-10-17 11:04:06 -04:00
  • 7fd5312b67 minor felsabbagh3 2019-10-17 10:50:36 -04:00
  • 95047fcadc Rename Stage that removes the need for forwarding felsabbagh3 2019-10-17 00:48:54 -04:00
  • 9a9afbbb6b Updated makefile felsabbagh3 2019-10-16 19:56:11 -04:00
  • 0690043a43 Still giving sc_time_stamp error felsabbagh3 2019-10-16 19:45:21 -04:00
  • 8bc3b8b0a5 Need to link SystemC for sc_time_stamp() felsabbagh3 2019-10-14 23:25:14 -04:00
  • 22f02820cf GPR back-end with mem felsabbagh3 2019-10-14 19:10:47 -04:00
  • ee83e6d8c8 Moved GPR to back-end felsabbagh3 2019-10-14 19:08:32 -04:00
  • 5680b997b5 Generate LIB files for rf2_32x128_wm1 Lingjun Zhu 2019-10-14 17:08:18 -04:00
  • f28cd286e6 Implemented the GPR model with the CLN28HPC memory block Lingjun Zhu 2019-10-13 20:27:28 -04:00
  • d5dad1c442 Updated the two-port GPR model Lingjun Zhu 2019-10-13 19:52:14 -04:00
  • 8af8c67299 Implemented the two-port GPR model Lingjun Zhu 2019-10-13 19:44:50 -04:00
  • b9d2e09d78 Move the memory models from Cache_Progress to Master branch Lingjun Zhu 2019-10-13 13:13:42 -04:00
  • e67310acfb New Warp Scheduler + VCD Enable felsabbagh3 2019-09-15 00:12:41 -04:00