Commit Graph

23 Commits

Author SHA1 Message Date
Blaise Tine
97739e9dcf RAM blocks inference fixes 2020-11-30 14:02:47 -08:00
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5758ef9ebf generic_register reset network optimization 2020-11-29 18:41:36 -08:00
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461be0880d fixed FPU-CSR data dependence 2020-11-25 09:05:38 -08:00
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34b650be94 fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug 2020-11-17 00:27:24 -08:00
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36ec603d17 fpga fixes: warp scheduler, fnmadd, fdiv, fsqrt 2020-09-08 07:05:26 -07:00
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49b86c4b2a SCOPE update 2020-09-05 10:52:59 -07:00
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42e3b6c45d fixed lmp_mult parameters, ram init filepath 2020-09-04 07:51:46 -07:00
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0a0b28aac0 minor update - 206-214 mhz 2020-08-29 05:14:08 -07:00
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ee81e81818 adding using serial divider to save area cost 2020-08-25 02:29:27 -07:00
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57971f6c76 decode op_mod optimization 2020-08-24 02:55:14 -07:00
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f292e5003d quartus build fixes 2020-08-23 22:04:46 -07:00
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0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
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6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
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65415d2bbc getting dogfood tests passing on Verilator! 2020-08-09 18:13:12 -04:00
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ffd9515881 added altera fpu modules 2020-08-05 15:53:59 -07:00
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8976100025 floating point support fixes 2020-07-28 04:19:46 -04:00
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7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
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1f63f9da25 new fpu implementation 2020-07-24 00:00:37 -04:00
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75e3c31b56 fpu implementation (part1) 2020-07-23 03:18:09 -07:00
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ff7f65bd1f opae build fixes 2020-07-21 05:44:13 -07:00
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dc7efbcfb4 pipeline refactoring 2020-07-21 05:22:47 -04:00
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577a5791dc pipeline refactoring 2020-07-20 08:04:04 -04:00
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25f66e6490 pipeline refactoring 2020-07-19 05:03:47 -04:00