Blaise Tine
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f12be56d7c
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fixed Verilator warnings
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2021-08-13 05:52:43 -04:00 |
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Blaise Tine
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c2b3aaa7d1
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enabling delayed tracing
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2021-08-12 20:05:43 -07:00 |
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Blaise Tine
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e0487e4555
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minor reset delay fix
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2021-07-16 21:31:46 -07:00 |
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Blaise Tine
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5c58f7eec6
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minor update
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2021-07-16 12:57:50 -07:00 |
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Blaise Tine
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65c1078158
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minor update
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2021-07-01 06:51:36 -04:00 |
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Blaise Tine
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93fee18d59
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minor update
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2021-07-01 02:59:44 -07:00 |
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Blaise Tine
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e8c01e18d8
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regression fixes
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2021-06-29 04:32:32 -04:00 |
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Blaise Tine
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d684a2e632
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application exit error handing
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2021-06-29 02:04:07 -04:00 |
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Blaise Tine
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7e0dc81cee
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minor update
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2021-06-23 04:19:13 -07:00 |
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Blaise Tine
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2372067817
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minor update
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2021-06-22 09:30:36 -07:00 |
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Blaise Tine
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6213b1a910
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vortex runtime console out implementation
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2021-06-15 04:01:44 -04:00 |
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Blaise Tine
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03406c0a3f
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project tests refactoring
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2021-06-13 17:42:04 -07:00 |
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Blaise Tine
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3cc1190cd7
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CSRs I/O refactoring
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2021-06-11 03:08:07 -07:00 |
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Blaise Tine
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a46d6cb606
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ebreak workaround for RISC-V tests
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2021-06-10 19:55:33 -07:00 |
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Blaise Tine
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3071fb7a29
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adding support for non-cacheable memory addressing
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2021-06-06 13:35:55 -07:00 |
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Blaise Tine
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df7d91d690
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more testing
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2021-05-26 15:29:39 -07:00 |
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Blaise Tine
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b3e54e66f8
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fixed compiler warnings
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2021-05-23 10:54:06 -07:00 |
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Blaise Tine
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269c06f7ea
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minor update
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2021-04-29 23:58:45 -07:00 |
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Blaise Tine
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95f057bc2e
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fpga build refactoring
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2021-04-29 06:17:28 -07:00 |
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Blaise Tine
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8543e3a8bf
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code refactoring
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2021-04-26 02:34:21 -07:00 |
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Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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Blaise Tine
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4cb98a25a7
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enabling 128-bit dram bus
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2021-04-24 00:31:27 -04:00 |
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Blaise Tine
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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5419859281
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fcvt fix
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2021-01-25 02:22:00 -08:00 |
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Blaise Tine
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ce9ef840d6
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minor updates
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2021-01-18 04:22:40 -08:00 |
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Blaise Tine
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ac2242b51f
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minor update
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2021-01-07 00:18:10 -08:00 |
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Blaise Tine
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146c285aa0
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minor update
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2021-01-06 19:59:04 -08:00 |
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Blaise Tine
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2b8435471a
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speeding up simulation using dedicated full dpi-based FPU core
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2021-01-06 18:44:06 -08:00 |
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Blaise Tine
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39bff921be
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cache bug fixes
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2021-01-05 05:04:49 -08:00 |
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Blaise Tine
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762b8e2e3e
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fixed cache mshr critical path
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2021-01-04 12:49:40 -05:00 |
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Blaise Tine
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4bc3b537bd
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fixed reset fan-out
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2021-01-03 20:06:36 -08:00 |
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Blaise Tine
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4815ab099c
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using single-port block ram for cache tags, restoring core reset signal
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2021-01-02 19:53:41 -08:00 |
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Blaise Tine
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703a861fe9
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added support for write-through cache, removed cache snooping support
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2020-12-23 23:51:02 -08:00 |
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Blaise Tine
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d956e268b9
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adding new performance counters (banks utilization and DRAM bus utilization)
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2020-12-22 12:33:45 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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dada72f830
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minor update
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2020-12-06 15:28:58 -08:00 |
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Blaise Tine
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b7a724410b
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update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)
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2020-12-03 07:30:19 -08:00 |
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Blaise Tine
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97739e9dcf
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RAM blocks inference fixes
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2020-11-30 14:02:47 -08:00 |
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Blaise Tine
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b85391389b
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rename MSRQ to MSHR
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2020-11-28 17:32:00 -05:00 |
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Blaise Tine
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00d7473268
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build warnings clean
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2020-11-28 14:59:13 -05:00 |
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Blaise Tine
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457f831435
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fixed scoreboard stall
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2020-11-28 03:14:20 -05:00 |
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Blaise Tine
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461be0880d
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fixed FPU-CSR data dependence
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2020-11-25 09:05:38 -08:00 |
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Blaise Tine
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664ce28426
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minor update
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2020-11-23 12:21:39 -08:00 |
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Blaise Tine
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2d4fef6dd6
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fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles
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2020-11-23 11:59:40 -08:00 |
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Blaise Tine
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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Blaise Tine
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e946d976e7
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constant integration updates
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2020-11-15 08:44:57 -08:00 |
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Blaise Tine
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5d58bf3d11
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fixed l3cache hang using memory arbiter in afu
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2020-11-15 06:36:32 -08:00 |
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Blaise Tine
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203a184008
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fixed bank_core_req_abr critical path
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2020-11-08 18:25:32 -08:00 |
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Blaise Tine
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5be1d85648
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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
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2020-11-02 01:50:12 -08:00 |
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