Commit Graph

130 Commits

Author SHA1 Message Date
Blaise Tine
7529f72c5d fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags 2020-10-20 05:32:55 -07:00
Blaise Tine
32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
Blaise Tine
309dd48fc6 scope bug fixes 2020-10-06 03:59:27 -04:00
Blaise Tine
4e1007e5b2 scope refactoring 2020-10-03 18:53:21 -04:00
Blaise Tine
42e3b6c45d fixed lmp_mult parameters, ram init filepath 2020-09-04 07:51:46 -07:00
Blaise Tine
af84e01856 minor update 2020-08-31 06:17:49 -07:00
Blaise Tine
0a0b28aac0 minor update - 206-214 mhz 2020-08-29 05:14:08 -07:00
Blaise Tine
efbe4a07ef serial divider optimization 2020-08-25 03:23:57 -07:00
Blaise Tine
ee81e81818 adding using serial divider to save area cost 2020-08-25 02:29:27 -07:00
Blaise Tine
f292e5003d quartus build fixes 2020-08-23 22:04:46 -07:00
Blaise Tine
1c9445745f fp_noncomp fixes 2020-08-23 16:53:28 -07:00
Blaise Tine
96f5432592 minor update 2020-08-22 13:56:07 -07:00
Blaise Tine
0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
Blaise Tine
6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
Blaise Tine
65415d2bbc getting dogfood tests passing on Verilator! 2020-08-09 18:13:12 -04:00
Blaise Tine
cd29362d10 fixed FPU handshake, optimized writeback's critical path 2020-08-07 10:11:54 -07:00
Blaise Tine
ffd9515881 added altera fpu modules 2020-08-05 15:53:59 -07:00
Blaise Tine
d8bdaa2b4e minor update 2020-08-01 14:38:31 -07:00
Blaise Tine
31ee824862 merged fpu_port branch 2020-07-31 17:13:22 -04:00
Blaise Tine
4bdab8903e merge 2020-07-31 16:49:59 -04:00
Blaise Tine
27e95530ef pipeline optimization 2020-07-30 03:06:01 -07:00
Blaise Tine
c2dd0a8b39 modelsim fixes && pipeline optimization 2020-07-28 14:20:23 -07:00
Blaise Tine
f3721c523f minor update 2020-07-28 06:02:32 -04:00
Blaise Tine
7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
Blaise Tine
dc7efbcfb4 pipeline refactoring 2020-07-21 05:22:47 -04:00
Blaise Tine
25f66e6490 pipeline refactoring 2020-07-19 05:03:47 -04:00
trmontgomery
ed3a0cfa4d added rsp map 2020-07-19 00:08:09 -04:00
Blaise Tine
bdfacf709c yosys synthesis refactoring 2020-07-10 18:56:41 -04:00
Blaise Tine
5d088d67c8 Gather FPGA perf stats 2020-07-01 09:30:12 -07:00
Blaise Tine
75d66dc335 fix sources.txt, run_ase.sh 2020-06-29 12:52:28 -07:00
Blaise Tine
a70562d386 set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18 2020-06-29 08:03:19 -07:00
felsabbagh3
e919e452b9 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2020-06-28 20:01:49 -07:00
felsabbagh3
21566cdcd7 Fixed Single Core with Optimizations 2020-06-28 19:38:36 -07:00
Blaise Tine
eb67788bf2 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2020-06-28 14:45:01 -07:00
Blaise Tine
27ea36440e multiplier fixes 2020-06-28 14:39:18 -07:00
felsabbagh3
ffb760cf73 Optimized cache writeback path by 1) VX_fair_arbiter and 2) Added a wb register between LSU and WB arbiter 2020-06-28 14:27:47 -07:00
Blaise Tine
baf7d3bb92 minor update 2020-06-27 17:46:45 -04:00
Blaise Tine
8302641510 fpga fixes 2020-06-27 14:03:20 -07:00
Blaise Tine
e6cc221a44 refactoring 2020-06-23 10:59:30 -07:00
Blaise Tine
0a01385a2c few updates 2020-06-23 09:28:24 -07:00
Blaise Tine
d3440de403 round robin arbiter + auto buffered queue + fixed dcache arbiter 2020-06-20 17:56:04 -04:00
Blaise Tine
68d9fc9a75 driver basic test and demo test refactoring 2020-06-19 09:12:07 -07:00
Blaise Tine
9850a1f890 minor fixes 2020-06-15 00:20:56 -07:00
Blaise Tine
75af29febb scope refactoring 2020-06-13 11:47:28 -07:00
Blaise Tine
d6b0ef2b3c scope refactoring + snoop invalidate 2020-06-12 00:04:31 -07:00
Blaise Tine
19f263c772 scope fixes 2020-06-09 20:49:36 -07:00
Blaise Tine
457783322b scope fixes 2020-06-09 07:03:52 -07:00
Blaise Tine
9575fe9a51 scope fixes 2020-06-08 06:54:47 -07:00
Blaise Tine
170c88f295 scope fixes 2020-06-08 04:25:28 -07:00
Blaise Tine
9ae38433fb VX_pipeline refactoring + logic analyzer 2020-06-06 01:52:44 -04:00