Santosh Raghav Srivatsan
|
e6eda67d0c
|
Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension
|
2021-12-06 18:55:13 -05:00 |
|
Santosh Raghav Srivatsan
|
f0dc04ad04
|
Added tests to commit. 64 bit simx still not working
|
2021-12-01 02:44:14 -05:00 |
|
Santosh Raghav Srivatsan
|
64d47f3637
|
Added support for RV64I instructions
|
2021-11-27 12:33:30 -05:00 |
|
Santosh Raghav Srivatsan
|
d1892bd6ec
|
Added support for a few RV64I instructions
|
2021-11-11 13:35:14 -05:00 |
|
Santosh Raghav Srivatsan
|
9cd8dec397
|
Extended register file to 64 bits
|
2021-11-08 17:54:16 -05:00 |
|
Blaise Tine
|
54bddeee9c
|
simulation framework refactoring
|
2021-10-09 10:20:42 -04:00 |
|