Blaise Tine
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7e0dc81cee
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minor update
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2021-06-23 04:19:13 -07:00 |
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Blaise Tine
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d80e1b28a3
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fixes for multi-channel memory support
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2021-05-20 05:36:09 -07:00 |
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Blaise Tine
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3e88a71801
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minor update
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2021-05-06 08:55:46 -07:00 |
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Blaise Tine
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6107bf8247
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minor fix
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2021-05-04 11:05:07 -07:00 |
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Blaise Tine
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bde6a69ea0
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adding support for multi-banks memory bus
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2021-05-04 07:32:03 -07:00 |
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Blaise Tine
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d504adb236
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afu mem controller refactoring
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2021-05-01 08:39:52 -07:00 |
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Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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Blaise Tine
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4cb98a25a7
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enabling 128-bit dram bus
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2021-04-24 00:31:27 -04:00 |
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Blaise Tine
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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Blaise Tine
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ed216ab39d
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minor updates
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2021-01-17 13:58:43 -08:00 |
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Blaise Tine
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fe64c47f60
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ccip write fix
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2021-01-14 22:49:06 -08:00 |
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Blaise Tine
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e770824d47
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fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
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2021-01-10 20:26:15 -08:00 |
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Blaise Tine
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06945533cf
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fixed l2/l3 caches related bugs
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2021-01-09 16:32:55 -08:00 |
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Blaise Tine
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d44144f72f
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FPU float<->int conversion optimization
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2020-12-29 15:37:45 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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12f7fcfa75
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adding missing files, buffering teh snoop forwarder
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2020-12-09 00:24:32 -08:00 |
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