Blaise Tine
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5419859281
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fcvt fix
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2021-01-25 02:22:00 -08:00 |
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Blaise Tine
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ce9ef840d6
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minor updates
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2021-01-18 04:22:40 -08:00 |
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Blaise Tine
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ac2242b51f
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minor update
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2021-01-07 00:18:10 -08:00 |
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Blaise Tine
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146c285aa0
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minor update
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2021-01-06 19:59:04 -08:00 |
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Blaise Tine
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2b8435471a
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speeding up simulation using dedicated full dpi-based FPU core
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2021-01-06 18:44:06 -08:00 |
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Blaise Tine
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39bff921be
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cache bug fixes
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2021-01-05 05:04:49 -08:00 |
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Blaise Tine
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762b8e2e3e
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fixed cache mshr critical path
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2021-01-04 12:49:40 -05:00 |
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Blaise Tine
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4bc3b537bd
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fixed reset fan-out
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2021-01-03 20:06:36 -08:00 |
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Blaise Tine
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4815ab099c
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using single-port block ram for cache tags, restoring core reset signal
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2021-01-02 19:53:41 -08:00 |
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Blaise Tine
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703a861fe9
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added support for write-through cache, removed cache snooping support
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2020-12-23 23:51:02 -08:00 |
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Blaise Tine
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d956e268b9
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adding new performance counters (banks utilization and DRAM bus utilization)
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2020-12-22 12:33:45 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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dada72f830
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minor update
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2020-12-06 15:28:58 -08:00 |
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Blaise Tine
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b7a724410b
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update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)
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2020-12-03 07:30:19 -08:00 |
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Blaise Tine
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97739e9dcf
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RAM blocks inference fixes
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2020-11-30 14:02:47 -08:00 |
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Blaise Tine
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b85391389b
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rename MSRQ to MSHR
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2020-11-28 17:32:00 -05:00 |
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Blaise Tine
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00d7473268
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build warnings clean
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2020-11-28 14:59:13 -05:00 |
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Blaise Tine
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457f831435
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fixed scoreboard stall
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2020-11-28 03:14:20 -05:00 |
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Blaise Tine
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461be0880d
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fixed FPU-CSR data dependence
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2020-11-25 09:05:38 -08:00 |
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Blaise Tine
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664ce28426
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minor update
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2020-11-23 12:21:39 -08:00 |
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Blaise Tine
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2d4fef6dd6
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fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles
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2020-11-23 11:59:40 -08:00 |
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Blaise Tine
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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Blaise Tine
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e946d976e7
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constant integration updates
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2020-11-15 08:44:57 -08:00 |
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Blaise Tine
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5d58bf3d11
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fixed l3cache hang using memory arbiter in afu
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2020-11-15 06:36:32 -08:00 |
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Blaise Tine
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203a184008
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fixed bank_core_req_abr critical path
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2020-11-08 18:25:32 -08:00 |
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Blaise Tine
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5be1d85648
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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
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2020-11-02 01:50:12 -08:00 |
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Blaise Tine
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4bd5ee2673
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fixed rtlsim regression
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2020-10-26 12:59:58 -04:00 |
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Blaise Tine
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43ae82e788
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vlsim fix, verilator fst trace, use ram optimization
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2020-10-25 16:40:50 -07:00 |
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Blaise Tine
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4e1007e5b2
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scope refactoring
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2020-10-03 18:53:21 -04:00 |
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Blaise Tine
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990b1585f1
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CI script updates
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2020-09-20 01:27:34 -04:00 |
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Blaise Tine
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c9d38c2b80
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CI script updates
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2020-09-20 00:17:42 -04:00 |
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Blaise Tine
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a8972af51e
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Merge branch 'master' of https://github.com/vortexgpgpu/vortex-dev
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2020-09-19 22:44:27 -04:00 |
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Blaise Tine
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f6f95e0c46
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mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
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2020-09-19 14:45:42 -04:00 |
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Malik Burton
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0646180059
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Modified testbench.cpp to assume passed for
runtime and isa tests.
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2020-09-19 11:24:53 -04:00 |
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Blaise Tine
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0fab1ddd92
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adding support for verilator-driven AFU driver: vlsim
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2020-09-08 13:05:26 -04:00 |
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Blaise Tine
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112d8ab815
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adding CSR support to rtlsim driver
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2020-09-04 06:51:31 -04:00 |
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Blaise Tine
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df711986bc
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FPU DPI fallback
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2020-08-31 09:19:55 -04:00 |
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Blaise Tine
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fde3f46798
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ibuffer optimization
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2020-08-26 04:44:36 -07:00 |
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MalikBurton
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de5eb4c8b5
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updated Makefile of riscv_tests/isa
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2020-08-11 13:55:36 -04:00 |
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Blaise Tine
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688c9892d5
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-08-07 10:12:29 -07:00 |
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Blaise Tine
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cd29362d10
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fixed FPU handshake, optimized writeback's critical path
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2020-08-07 10:11:54 -07:00 |
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MalikBurton
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87220f2d29
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benchmarks/riscv_tests Makefiles and modified testbench.cpp
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2020-08-07 12:54:03 -04:00 |
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Blaise Tine
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b8cd3b0b28
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gpr pipeline optimization
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2020-08-01 12:38:30 -04:00 |
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Blaise Tine
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31ee824862
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merged fpu_port branch
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2020-07-31 17:13:22 -04:00 |
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Blaise Tine
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4bdab8903e
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merge
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2020-07-31 16:49:59 -04:00 |
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Blaise Tine
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c9755a0c48
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lkg build with pipeline + FPU fixes
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2020-07-31 09:29:44 -04:00 |
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MalikBurton
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8abc15d266
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All runtime tests can be run from runtime/tests Makefile
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2020-07-28 18:30:20 -04:00 |
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Blaise Tine
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c2dd0a8b39
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modelsim fixes && pipeline optimization
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2020-07-28 14:20:23 -07:00 |
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MalikBurton
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7fc7bc0cab
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Runtime tests and riscv tests are runnable
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2020-07-28 16:04:27 -04:00 |
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Blaise Tine
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8976100025
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floating point support fixes
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2020-07-28 04:19:46 -04:00 |
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