Blaise Tine
|
9f34b2944c
|
code refactoring for Vivado, sv2v, and yosys compatibility
|
2021-09-27 08:55:10 -04:00 |
|
Blaise Tine
|
18172fa611
|
AXI memory bus support
|
2021-09-10 01:36:01 -07:00 |
|
Blaise Tine
|
a60bfc5e01
|
extending tracing feature for advanced debugging
|
2021-08-15 05:10:46 -07:00 |
|
Blaise Tine
|
f12be56d7c
|
fixed Verilator warnings
|
2021-08-13 05:52:43 -04:00 |
|
Blaise Tine
|
c2b3aaa7d1
|
enabling delayed tracing
|
2021-08-12 20:05:43 -07:00 |
|
Blaise Tine
|
e0487e4555
|
minor reset delay fix
|
2021-07-16 21:31:46 -07:00 |
|
Blaise Tine
|
d684a2e632
|
application exit error handing
|
2021-06-29 02:04:07 -04:00 |
|
Blaise Tine
|
7e0dc81cee
|
minor update
|
2021-06-23 04:19:13 -07:00 |
|
Blaise Tine
|
2372067817
|
minor update
|
2021-06-22 09:30:36 -07:00 |
|
Blaise Tine
|
6213b1a910
|
vortex runtime console out implementation
|
2021-06-15 04:01:44 -04:00 |
|
Blaise Tine
|
3cc1190cd7
|
CSRs I/O refactoring
|
2021-06-11 03:08:07 -07:00 |
|
Blaise Tine
|
a46d6cb606
|
ebreak workaround for RISC-V tests
|
2021-06-10 19:55:33 -07:00 |
|
Blaise Tine
|
3071fb7a29
|
adding support for non-cacheable memory addressing
|
2021-06-06 13:35:55 -07:00 |
|
Blaise Tine
|
df7d91d690
|
more testing
|
2021-05-26 15:29:39 -07:00 |
|
Blaise Tine
|
8543e3a8bf
|
code refactoring
|
2021-04-26 02:34:21 -07:00 |
|
Blaise Tine
|
8410c49f53
|
code refactoring: DRAM => MEM renaming
|
2021-04-26 00:58:48 -07:00 |
|
Blaise Tine
|
146c285aa0
|
minor update
|
2021-01-06 19:59:04 -08:00 |
|
Blaise Tine
|
2b8435471a
|
speeding up simulation using dedicated full dpi-based FPU core
|
2021-01-06 18:44:06 -08:00 |
|
Blaise Tine
|
39bff921be
|
cache bug fixes
|
2021-01-05 05:04:49 -08:00 |
|
Blaise Tine
|
762b8e2e3e
|
fixed cache mshr critical path
|
2021-01-04 12:49:40 -05:00 |
|
Blaise Tine
|
4bc3b537bd
|
fixed reset fan-out
|
2021-01-03 20:06:36 -08:00 |
|
Blaise Tine
|
4815ab099c
|
using single-port block ram for cache tags, restoring core reset signal
|
2021-01-02 19:53:41 -08:00 |
|
Blaise Tine
|
703a861fe9
|
added support for write-through cache, removed cache snooping support
|
2020-12-23 23:51:02 -08:00 |
|
Blaise Tine
|
d956e268b9
|
adding new performance counters (banks utilization and DRAM bus utilization)
|
2020-12-22 12:33:45 -08:00 |
|
Blaise Tine
|
4bbd7bf408
|
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
|
2020-12-19 02:45:06 -08:00 |
|
Blaise Tine
|
dada72f830
|
minor update
|
2020-12-06 15:28:58 -08:00 |
|
Blaise Tine
|
b7a724410b
|
update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)
|
2020-12-03 07:30:19 -08:00 |
|
Blaise Tine
|
457f831435
|
fixed scoreboard stall
|
2020-11-28 03:14:20 -05:00 |
|
Blaise Tine
|
461be0880d
|
fixed FPU-CSR data dependence
|
2020-11-25 09:05:38 -08:00 |
|
Blaise Tine
|
664ce28426
|
minor update
|
2020-11-23 12:21:39 -08:00 |
|
Blaise Tine
|
2d4fef6dd6
|
fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles
|
2020-11-23 11:59:40 -08:00 |
|
Blaise Tine
|
1795980a52
|
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
|
2020-11-21 09:47:56 -08:00 |
|
Blaise Tine
|
203a184008
|
fixed bank_core_req_abr critical path
|
2020-11-08 18:25:32 -08:00 |
|
Blaise Tine
|
5be1d85648
|
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
|
2020-11-02 01:50:12 -08:00 |
|
Blaise Tine
|
4bd5ee2673
|
fixed rtlsim regression
|
2020-10-26 12:59:58 -04:00 |
|
Blaise Tine
|
43ae82e788
|
vlsim fix, verilator fst trace, use ram optimization
|
2020-10-25 16:40:50 -07:00 |
|
Blaise Tine
|
f6f95e0c46
|
mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
|
2020-09-19 14:45:42 -04:00 |
|
Blaise Tine
|
0fab1ddd92
|
adding support for verilator-driven AFU driver: vlsim
|
2020-09-08 13:05:26 -04:00 |
|
Blaise Tine
|
112d8ab815
|
adding CSR support to rtlsim driver
|
2020-09-04 06:51:31 -04:00 |
|
Blaise Tine
|
fde3f46798
|
ibuffer optimization
|
2020-08-26 04:44:36 -07:00 |
|
Blaise Tine
|
b8cd3b0b28
|
gpr pipeline optimization
|
2020-08-01 12:38:30 -04:00 |
|
Blaise Tine
|
c9755a0c48
|
lkg build with pipeline + FPU fixes
|
2020-07-31 09:29:44 -04:00 |
|
Blaise Tine
|
f01afcc5cd
|
floating point support fixes + riscv-tests update
|
2020-07-28 02:19:11 -04:00 |
|
Blaise Tine
|
e0a9089647
|
floating point support fixes
|
2020-07-27 16:01:56 -04:00 |
|
Blaise Tine
|
7c86b68977
|
pipeline refactoring: centralized issue buffer
|
2020-07-26 11:21:08 -04:00 |
|
Blaise Tine
|
fb44de8017
|
fixed simulator leak
|
2020-07-21 06:17:41 -07:00 |
|
Blaise Tine
|
577a5791dc
|
pipeline refactoring
|
2020-07-20 08:04:04 -04:00 |
|
Blaise Tine
|
25f66e6490
|
pipeline refactoring
|
2020-07-19 05:03:47 -04:00 |
|
Blaise Tine
|
d33916f1e0
|
minor update
|
2020-06-29 00:38:59 -07:00 |
|
Blaise Tine
|
8a306de02d
|
runtime static library
|
2020-06-27 14:13:13 -04:00 |
|