 Blaise Tine
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2216a3059d
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minor update
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2021-04-27 05:52:01 -04:00 |
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Blaise Tine
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8543e3a8bf
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code refactoring
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2021-04-26 02:34:21 -07:00 |
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Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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Blaise Tine
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4cb98a25a7
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enabling 128-bit dram bus
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2021-04-24 00:31:27 -04:00 |
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Blaise Tine
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4bc3b537bd
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fixed reset fan-out
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2021-01-03 20:06:36 -08:00 |
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Blaise Tine
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4815ab099c
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using single-port block ram for cache tags, restoring core reset signal
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2021-01-02 19:53:41 -08:00 |
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Blaise Tine
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e4a00dd0d9
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fixed loader script stack setup
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2020-12-31 22:37:20 -05:00 |
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Blaise Tine
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2d4fef6dd6
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fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles
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2020-11-23 11:59:40 -08:00 |
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Blaise Tine
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5be1d85648
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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
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2020-11-02 01:50:12 -08:00 |
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Blaise Tine
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43ae82e788
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vlsim fix, verilator fst trace, use ram optimization
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2020-10-25 16:40:50 -07:00 |
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Blaise Tine
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38303cdc2f
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vlsim: host_buffer optimization
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2020-09-09 17:53:31 -04:00 |
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Blaise Tine
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fba2fa03c7
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fixed new AFU Driver bugs - now functional
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2020-09-09 17:05:48 -04:00 |
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Blaise Tine
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0fab1ddd92
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adding support for verilator-driven AFU driver: vlsim
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2020-09-08 13:05:26 -04:00 |
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