Commit Graph
16 Commits
Author SHA1 Message Date
Hansung Kim 3e67ddd6c6 tensor: Properly guard tc_rf_if for non-hopper 2024-10-27 17:55:09 -07:00
Hansung Kim 1bc4afe2bb tensor: Bore tensor regfile IO to execute units 2024-10-24 20:32:18 -07:00
Richard Yan 155cbb0abc tc rf read port 2024-10-24 16:51:15 -07:00
Hansung Kim 5a0ee98a61 Remove duplicate port connection 2024-05-03 15:07:24 -07:00
Hansung Kim 675e8ea130 Merge branch 'tensor_core' into rtl 2024-05-01 16:18:14 -07:00
Hansung Kim 978b1fe2d0 Add operands stage with duplicated RF for rs1/2/3 2024-04-15 16:45:59 -07:00
Hansung Kim 87b966a5fa Add perf counter for stall by any operand hazard 2024-04-15 01:01:26 -07:00
Hansung Kim 62c7d1f4cf Report any fire cycles from scoreboard as well 2024-03-29 12:23:15 -07:00
Hansung Kim 3e6a9a6104 Expose scoreboard fires to perf interface 2024-03-23 01:06:40 -07:00
Hansung Kim 83e151a189 Add valid / fire / cycles-issued perf counters to dispatch 2024-03-23 00:01:15 -07:00
joshua f9b4509936 initial tensor core 2024-03-20 02:46:00 -07:00
Blaise Tine e217bc2c23 adding tracking for SFU stalls 2023-12-28 12:12:11 -08:00
Blaise Tine c7a81d1493 adding sockets support to simx and cache subsystem refactoring
minor update

minor update

minor updates
2023-12-20 15:16:12 -08:00
Blaise Tine c6845a4c8d profiling timing optimization
minor update

minor update

minor update
2023-12-18 04:43:10 -08:00
Blaise Tine 24973ffca0 scoreboard optimization & profiling 2023-11-27 05:53:36 -08:00
Blaise Tine d47cccc157 Vortex 2.0 changes:
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00