Commit Graph

125 Commits

Author SHA1 Message Date
Blaise Tine
7c384eaf7f fixed snoop forwarding hang 2020-11-09 20:02:33 -08:00
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f8d54c6994 fixed cache_core_rsp_merge unit 2020-11-09 02:10:35 -08:00
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203a184008 fixed bank_core_req_abr critical path 2020-11-08 18:25:32 -08:00
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10505caae1 refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2 2020-11-08 01:31:46 -08:00
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ba81d76e02 cache refactoring - phase 2 2020-11-03 04:51:40 -08:00
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5be1d85648 cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count 2020-11-02 01:50:12 -08:00
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3fe31fc337 fixed afu to cpu mempcy hang 2020-10-28 14:19:13 -07:00
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9a9f7955f0 basic test timing + scope tracing ccip 2020-10-27 17:04:04 -04:00
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48897d9778 minor update 2020-10-25 18:29:25 -07:00
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43ae82e788 vlsim fix, verilator fst trace, use ram optimization 2020-10-25 16:40:50 -07:00
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e6466b887c minor update 2020-10-20 08:45:21 -07:00
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7529f72c5d fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags 2020-10-20 05:32:55 -07:00
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301cc45740 scope fixes 2020-10-14 09:19:26 -07:00
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58b8e82908 scope fixes ... 2020-10-13 17:09:22 -04:00
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4bfc4ee78f scope fixes 2020-10-13 08:44:55 -07:00
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32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
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309dd48fc6 scope bug fixes 2020-10-06 03:59:27 -04:00
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4e1007e5b2 scope refactoring 2020-10-03 18:53:21 -04:00
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91f348c61a adding prebuilt CI script 2020-09-19 16:08:28 -04:00
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f6f95e0c46 mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL 2020-09-19 14:45:42 -04:00
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80f929eb61 fixed build warnings; sgemm Makefile 2020-09-10 13:39:34 -04:00
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fba2fa03c7 fixed new AFU Driver bugs - now functional 2020-09-09 17:05:48 -04:00
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bf7b0cf340 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2020-09-08 13:05:47 -04:00
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0fab1ddd92 adding support for verilator-driven AFU driver: vlsim 2020-09-08 13:05:26 -04:00
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36ec603d17 fpga fixes: warp scheduler, fnmadd, fdiv, fsqrt 2020-09-08 07:05:26 -07:00
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75c98c6ea3 fmadd fix 2020-09-06 01:20:22 -07:00
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49b86c4b2a SCOPE update 2020-09-05 10:52:59 -07:00
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42e3b6c45d fixed lmp_mult parameters, ram init filepath 2020-09-04 07:51:46 -07:00
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b82f5a9011 fix ci bui;d 2020-09-01 10:45:44 -07:00
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c63217f67d fixed SCOPE interface 2020-09-01 05:20:13 -07:00
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0a45a8beb3 minor update 2020-09-01 00:56:10 -07:00
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ee81e81818 adding using serial divider to save area cost 2020-08-25 02:29:27 -07:00
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f292e5003d quartus build fixes 2020-08-23 22:04:46 -07:00
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96f5432592 minor update 2020-08-22 13:56:07 -07:00
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0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
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6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
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65415d2bbc getting dogfood tests passing on Verilator! 2020-08-09 18:13:12 -04:00
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ffd9515881 added altera fpu modules 2020-08-05 15:53:59 -07:00
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d8bdaa2b4e minor update 2020-08-01 14:38:31 -07:00
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b8cd3b0b28 gpr pipeline optimization 2020-08-01 12:38:30 -04:00
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836a735555 minor updates 2020-07-31 13:39:52 -07:00
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c2dd0a8b39 modelsim fixes && pipeline optimization 2020-07-28 14:20:23 -07:00
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1c9846d10b delete sources.txt 2020-07-28 03:20:20 -07:00
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7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
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ff7f65bd1f opae build fixes 2020-07-21 05:44:13 -07:00
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bdfacf709c yosys synthesis refactoring 2020-07-10 18:56:41 -04:00
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5d088d67c8 Gather FPGA perf stats 2020-07-01 09:30:12 -07:00
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83a1695c73 OPAE CSR access 2020-06-30 18:14:06 -07:00
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582a00d690 adding OPAE CSR support 2020-06-30 10:05:57 -07:00
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2de61b5982 get device caps from CSRs 2020-06-30 00:08:23 -07:00