6 Commits

Author	SHA1	Message	Date
felsabbagh3	ccbb2acab5	LSU+EXU minor	2019-10-17 22:38:09 -04:00
felsabbagh3	6779d0fade	Instruction Multiplex LSU/EXU 1 cycle DONE	2019-10-17 22:29:21 -04:00
Lingjun Zhu	d164ebfbc6	Added log file of synthesis, too many registers are removed	2019-10-17 14:25:54 -04:00
Lingjun Zhu	a4d6ada16d	Fixed the issues of memory during synthesis	2019-10-17 14:18:52 -04:00
Shim	78e4067013	added log file	2019-10-17 14:00:22 -04:00
Shim	0bea82a2c3	added tcl file	2019-10-17 11:55:18 -04:00