Commit Graph

27 Commits

Author SHA1 Message Date
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cc259f60f6 minor update 2021-08-11 15:39:21 -07:00
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90fa9eee7d minor update 2021-08-08 18:35:05 -07:00
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91d4419fae new regression tests 2021-08-02 16:05:33 -07:00
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6f0b5865e2 minor update 2021-07-25 02:35:34 -07:00
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152d807301 parallelizing continious integration 2021-07-20 12:12:11 -07:00
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5c40422e4f dcache response bus optimization 2021-07-12 10:14:48 -07:00
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d2f9c66840 minor update 2021-06-29 03:50:01 -07:00
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e8c01e18d8 regression fixes 2021-06-29 04:32:32 -04:00
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1ea738ed26 lkg build 2021-06-25 16:28:10 -07:00
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2372067817 minor update 2021-06-22 09:30:36 -07:00
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cadff791ab test layout fixes 2021-06-13 17:59:06 -07:00
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03406c0a3f project tests refactoring 2021-06-13 17:42:04 -07:00
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3071fb7a29 adding support for non-cacheable memory addressing 2021-06-06 13:35:55 -07:00
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df7d91d690 more testing 2021-05-26 15:29:39 -07:00
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9b120e3bb4 minor update 2021-05-24 20:05:36 -07:00
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c81b1173b8 minor update 2021-05-24 18:20:46 -07:00
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6107bf8247 minor fix 2021-05-04 11:05:07 -07:00
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bac53e4ae1 minor update 2021-05-02 11:05:49 -07:00
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d504adb236 afu mem controller refactoring 2021-05-01 08:39:52 -07:00
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95f057bc2e fpga build refactoring 2021-04-29 06:17:28 -07:00
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8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
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4cb98a25a7 enabling 128-bit dram bus 2021-04-24 00:31:27 -04:00
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41413a51ba testing no-shared memory mode 2021-04-01 12:37:40 -07:00
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3a266fc792 adding compiler tests to regression suite 2021-03-09 05:01:56 -08:00
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907e6868cd simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite 2021-03-08 23:58:33 -08:00
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700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
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6a6711b735 minor update 2021-02-04 09:11:46 -08:00