cb912d3b8b
Add Blackwell tensor RTL scaffolding
2026-04-25 10:15:31 +08:00
Hansung Kim
4376bd33a2
tensor: Decode rs1/rs2 of HGMMA for smem addresses
2024-10-28 19:41:37 -07:00
Hansung Kim
f7f23e0c05
tensor: Doc update
2024-10-11 18:00:36 -07:00
Hansung Kim
408a9b5d2a
tensor: Write stall logic for hgmma_wait
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HGMMA_WAIT instruction stalls at issue when inuse_tensor is set, which
is done by the previous HGMMA insn. Currently inuse_tensor is never set
back to zero.
2024-10-11 17:18:01 -07:00
Hansung Kim
58c9761829
Revert decode change for hopper
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Share the same insn as non-hopper TC.
2024-10-09 21:53:04 -07:00
Hansung Kim
4cac1adf7d
Add dummy code for decoupled Hopper tensor core
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Define EXT_T_HOPPER that, when EXT_T_ENABLE is defined, distinguishes
whether to instantiate core-coupled Volta-style or decoupled
Hopper-style Tensor Core.
2024-10-07 17:10:59 -07:00
Hansung Kim
1410b39143
Disable trace during the very start of simulation
2024-08-13 16:01:29 -07:00
Hansung Kim
9caafb2d8a
tensor: Decode rd of macro-op to designate additional accumulator
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This is useful when you want to have the tensor core output to multiple
accumulator registers, e.g. when doing outer product within the RF.
2024-05-31 19:17:56 -07:00
Hansung Kim
675e8ea130
Merge branch 'tensor_core' into rtl
2024-05-01 16:18:14 -07:00
joshua
f9b4509936
initial tensor core
2024-03-20 02:46:00 -07:00
Hansung Kim
8317a3fbe5
Fix fence by disallowing x-initialization instead of all-0 mask
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Setting mem_req_mask to all-zero triggers an assertion error in
mem_scheduler. Instead, disallow initialize-by-x in instruction decode
which is the source of x-propagation. Since this seems to only happen
in VCS, define-gate it accordingly.
This reverts commit a15f4fd483
2024-03-07 17:39:18 -08:00
Hansung Kim
b63333a4ec
Merge remote-tracking branch 'upstream/master' into vortex2
2024-03-07 14:45:48 -08:00
joshua
beb3dce46d
integer reduction unit
2024-03-06 01:39:17 -08:00
Blaise Tine
8ab7c590fd
disabling fetch's deadlock check when L1 caches are present
2024-01-31 06:16:54 -08:00
Hansung Kim
f41b50fc07
Define DBG_TRACE_CORE_PIPELINE_VCS for selective debug trace
2023-11-27 16:05:15 -08:00
Blaise Tine
d47cccc157
Vortex 2.0 changes:
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+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
