Commit Graph

55 Commits

Author SHA1 Message Date
Blaise Tine
c49f01b769 snooping response handling 2020-05-11 22:55:44 -04:00
Blaise Tine
cc84e0691c multicore fix 2020-05-10 08:30:04 -04:00
Blaise Tine
c2e9240b7d OPAE rtl fixes 2020-05-08 08:28:28 -07:00
Blaise Tine
de9fc68ccc opae fixes 2020-05-06 21:14:53 -07:00
Blaise Tine
330bbc4f56 rtl gpr multicore fix 2020-05-06 09:05:10 -04:00
Blaise Tine
b1fdf0a947 fix rtl gpr zero 2020-05-06 05:25:20 -04:00
Blaise Tine
f142afac80 rtl refactoring 2020-05-04 20:12:05 -04:00
Blaise Tine
69f607b73e rtl refactoring 2020-05-03 17:10:02 -04:00
Blaise Tine
a1dc90b951 rtl cache refactory 2020-04-30 17:12:18 -04:00
Tine, Blaise
016a4fdb60 Delete basic 2020-04-23 06:24:00 -04:00
Tine, Blaise
99bcc91a70 Delete demo 2020-04-23 06:23:47 -04:00
Blaise Tine
77a52ea20b optimized opae cci to dev memcpy using double buffering and request window to work around unordered read requests 2020-04-23 01:30:45 -07:00
Blaise Tine
d79e36912f fix opae build 2020-04-20 12:51:42 -07:00
Blaise Tine
a0e15af0dc RTL code refactoring 2020-04-20 13:01:42 -04:00
Blaise Tine
e8a4923eb4 RTL code refactoring 2020-04-20 12:09:30 -04:00
Blaise Tine
885869df4a adding DEBUG MACROS 2020-04-19 04:59:52 -04:00
Blaise Tine
9b476f1e17 RTL code refactoring 2020-04-19 03:38:00 -04:00
Blaise Tine
31f906f9fd fixed all build warnings 2020-04-16 10:22:46 -04:00
Blaise Tine
81745f08c9 added config.vh 2020-04-16 07:49:19 -04:00
Blaise Tine
12dc4d6874 refactoring fixes 2020-04-14 19:39:59 -04:00
Blaise Tine
fc155e1223 project directories reorganization 2020-04-14 06:35:20 -04:00
Blaise Tine
97a31401f7 rename driver dummy to stub 2020-04-10 22:40:58 -04:00
Blaise Tine
217dfb48ef adding README for OPAE hw 2020-04-08 11:44:06 -04:00
codetector
829042f472 add test runner script to run rtlsim benchmarks 2020-04-06 01:54:33 +00:00
codetector
dc5a4604cf Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis 2020-04-05 16:38:47 -04:00
Blaise Tine
30770b5026 minor updates 2020-04-05 01:16:54 -07:00
Blaise Tine
18f1350fdf update 2020-04-05 01:38:11 -04:00
Blaise Tine
256dec4768 changing demo to use addition 2020-04-05 01:32:57 -04:00
Blaise Tine
0a8d829f15 basic test update 2020-04-04 09:07:04 -04:00
Blaise Tine
07ec0ef344 OPAE hw snooping fixes 2020-04-04 05:07:45 -07:00
Blaise Tine
1f63139ce5 fix RTL code undefined variables 2020-04-03 22:59:40 -07:00
codetector
9ee12d4a01 Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis 2020-04-03 14:36:52 -04:00
Blaise Tine
f590d6acc8 minor update 2020-04-02 20:09:08 -07:00
Blaise Tine
bc6b2969ef minor opae hw fixed 2020-04-02 15:41:12 -07:00
codetector
c6319a0dbd more gitignore update 2020-04-02 14:16:02 -04:00
codetector
b9e5612949 fix gitignore 2020-04-02 14:13:48 -04:00
Blaise Tine
6463cca529 extending basic test 2020-04-02 08:46:32 -07:00
Blaise Tine
efd3c1d154 udpate 2020-04-02 06:51:11 -04:00
Blaise Tine
f7b7c509d5 udpate 2020-04-02 05:16:13 -04:00
Blaise Tine
7e4399e3ac OPAE HW full redesign - basic test passing 2020-04-02 05:10:51 -04:00
Blaise Tine
e92c4b6774 enable rtl sim dram stalls 2020-03-31 02:38:18 -04:00
Blaise Tine
2eb19e23c2 refactor RTL simulator 2020-03-30 01:53:34 -04:00
Blaise Tine
2d198a32c7 update 2020-03-29 23:18:26 -04:00
Blaise Tine
ce0cc44d11 update 2020-03-29 05:24:40 -04:00
Blaise Tine
c57de94b5c minor update 2020-03-29 01:17:09 -04:00
Blaise Tine
002d8fbec9 minor update 2020-03-29 00:40:02 -04:00
Blaise Tine
c8a6470595 redesigned driver demo, fixed startup code, removed --cpu from simx, 2020-03-29 00:38:17 -04:00
Blaise Tine
2d5cf89e00 update 2020-03-28 02:40:38 -04:00
Blaise Tine
cff762c435 adding opencl runtime and compiler tools 2020-03-28 00:35:54 -04:00
Blaise Tine
550d96a73c rtlsim driver works with Vortex! 2020-03-27 21:54:55 -04:00