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bb1ceffadd
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rebase master update
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2021-07-30 21:03:14 -07:00 |
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7d01be367c
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reset network refactoring
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2021-07-15 11:34:55 -07:00 |
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d504adb236
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afu mem controller refactoring
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2021-05-01 08:39:52 -07:00 |
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1e2da696ce
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arrays logging
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2021-04-02 02:20:15 -07:00 |
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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3c37db877a
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cache specialization for in-order DRAM reponses
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2021-02-13 20:23:29 -08:00 |
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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2d69ca5d67
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scratchpad optimization for stack access using custom bank offset aligned to stack size
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2021-01-02 16:00:00 -05:00 |
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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725322807e
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fixed DRAM response backpressure inside Cache
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2020-11-10 05:24:57 -08:00 |
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3fe31fc337
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fixed afu to cpu mempcy hang
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2020-10-28 14:19:13 -07:00 |
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43ae82e788
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vlsim fix, verilator fst trace, use ram optimization
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2020-10-25 16:40:50 -07:00 |
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7529f72c5d
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fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags
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2020-10-20 05:32:55 -07:00 |
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32da50816f
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scope refactoring: adding modules definitions to VCD trace
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2020-10-12 23:26:02 -04:00 |
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309dd48fc6
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scope bug fixes
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2020-10-06 03:59:27 -04:00 |
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4e1007e5b2
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scope refactoring
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2020-10-03 18:53:21 -04:00 |
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0a0b28aac0
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minor update - 206-214 mhz
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2020-08-29 05:14:08 -07:00 |
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0b355f228e
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ibuffer addition
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2020-08-22 00:22:04 -07:00 |
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6c12391338
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pipeline refactoring - fmax >= 222 mhz
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2020-08-14 21:50:14 -07:00 |
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27e95530ef
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pipeline optimization
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2020-07-30 03:06:01 -07:00 |
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c2dd0a8b39
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modelsim fixes && pipeline optimization
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2020-07-28 14:20:23 -07:00 |
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