Commit Graph

71 Commits

Author SHA1 Message Date
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bb1ceffadd rebase master update 2021-07-30 21:03:14 -07:00
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382585d33d minor update 2021-07-17 07:22:16 -07:00
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b99fb41d52 minor update 2021-07-08 01:31:12 -07:00
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10e9ee124b using onehot multiplexer to reduce critical path 2021-07-08 00:26:59 -07:00
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93fee18d59 minor update 2021-07-01 02:59:44 -07:00
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201aa2c6ad minor udpate 2021-06-28 09:14:06 -07:00
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fb805c1eed minor update 2021-06-28 06:50:43 -07:00
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c6afc35989 adding data fence support 2021-06-28 06:12:18 -07:00
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6ae2f5199d decode optimization 2021-06-28 05:06:30 -07:00
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5cfd6e6f82 minor updates 2021-04-04 04:04:41 -07:00
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d522611ee2 minor update 2021-04-03 05:07:00 -07:00
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a75accf6ed minor update 2021-04-01 23:31:55 -07:00
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638614fd6d decode optimization 2021-04-01 19:08:15 -07:00
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062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
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ad06408044 minor update 2021-03-01 01:51:25 -08:00
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b441870789 rename use_imm and use_PC 2021-03-01 00:38:46 -08:00
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e3a11e4a5c minor fix 2021-02-28 14:18:43 -08:00
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8a9a67aa5a minor update 2021-02-27 21:54:55 -08:00
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f5a17bd1a9 decode optimization and refactoring 2021-02-27 18:21:41 -08:00
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34ce0b8e89 minor update 2021-02-23 20:54:03 -08:00
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700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
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1792571e1b minor update 2021-02-22 13:30:45 -08:00
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6d7692da37 minor fix. 2021-02-21 03:37:36 -08:00
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9eed48435c instruction decode optimization 2021-02-14 00:19:54 -08:00
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98945df5ae minor updates 2021-01-17 12:50:07 -08:00
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7c4823e65c fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests 2021-01-11 23:55:09 -08:00
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b459192dec critical path optimization - fpga fmax @4c = ~212 mhz 2020-12-26 03:28:32 -08:00
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13a5370254 register file refactoring 2020-12-05 01:40:50 -08:00
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74c9e9ad1f minor update 2020-12-01 10:42:14 -08:00
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4c6a74fa87 cache refactoring - phase 3 - added dedicated pipeline stage for tag access 2020-11-04 03:21:30 -08:00
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7529f72c5d fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags 2020-10-20 05:32:55 -07:00
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49b86c4b2a SCOPE update 2020-09-05 10:52:59 -07:00
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ee81e81818 adding using serial divider to save area cost 2020-08-25 02:29:27 -07:00
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df25bae456 optimize warp_sched 2020-08-24 05:36:00 -07:00
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57971f6c76 decode op_mod optimization 2020-08-24 02:55:14 -07:00
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0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
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6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
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65415d2bbc getting dogfood tests passing on Verilator! 2020-08-09 18:13:12 -04:00
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b8cd3b0b28 gpr pipeline optimization 2020-08-01 12:38:30 -04:00
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c9755a0c48 lkg build with pipeline + FPU fixes 2020-07-31 09:29:44 -04:00
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27e95530ef pipeline optimization 2020-07-30 03:06:01 -07:00
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c2dd0a8b39 modelsim fixes && pipeline optimization 2020-07-28 14:20:23 -07:00
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ff12393998 floating point support fixes 2020-07-27 04:53:13 -04:00
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7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
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1f63f9da25 new fpu implementation 2020-07-24 00:00:37 -04:00
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75e3c31b56 fpu implementation (part1) 2020-07-23 03:18:09 -07:00
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dc7efbcfb4 pipeline refactoring 2020-07-21 05:22:47 -04:00
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e2100e9e87 pipeline refactoring 2020-07-20 09:38:54 -04:00
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25f66e6490 pipeline refactoring 2020-07-19 05:03:47 -04:00
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77c3b2d45f lsu_unit refactoring to reduce critical path 2020-07-10 11:23:34 -07:00