Commit Graph

47 Commits

Author SHA1 Message Date
Blaise Tine
bb1ceffadd rebase master update 2021-07-30 21:03:14 -07:00
Blaise Tine
b0d8adc82b minor update 2021-07-16 06:44:28 -07:00
Blaise Tine
6ae2f5199d decode optimization 2021-06-28 05:06:30 -07:00
Blaise Tine
3cc1190cd7 CSRs I/O refactoring 2021-06-11 03:08:07 -07:00
Blaise Tine
8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
Blaise Tine
d808aa2735 perf counters generic size 2021-04-25 21:15:24 -07:00
Blaise Tine
0e3872ee94 floating-point CSR fix 2021-03-01 01:46:41 -08:00
Blaise Tine
e64996946d using 44-bit perf counters - aligned with DSP counters width 2021-02-28 02:05:47 -08:00
Blaise Tine
700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
Blaise Tine
7c4823e65c fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests 2021-01-11 23:55:09 -08:00
Blaise Tine
30d950ada2 vx_spawn_warps redesign using opencl's style scheduler 2021-01-01 14:13:48 -05:00
Blaise Tine
e4a00dd0d9 fixed loader script stack setup 2020-12-31 22:37:20 -05:00
Blaise Tine
d956e268b9 adding new performance counters (banks utilization and DRAM bus utilization) 2020-12-22 12:33:45 -08:00
Blaise Tine
fe07ca9aee minor update 2020-12-09 05:49:02 -08:00
Blaise Tine
d5438fd591 merging perf counters 2020-12-08 21:02:39 -08:00
Xandy Liu
1595ff08e2 PERF pipeline stalls and cache 2020-12-08 01:14:41 -05:00
Blaise Tine
ac1883a13f tabs cleanup 2020-11-28 17:08:01 -05:00
Blaise Tine
461be0880d fixed FPU-CSR data dependence 2020-11-25 09:05:38 -08:00
Blaise Tine
2e0f51af80 fixed instr/cycle perf counter 2020-11-12 11:41:25 -08:00
Blaise Tine
b14007f930 pipeline optimization: fixed GPR fanout delay to execute units 2020-11-07 02:01:21 -08:00
Blaise Tine
5be1d85648 cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count 2020-11-02 01:50:12 -08:00
Blaise Tine
ee81e81818 adding using serial divider to save area cost 2020-08-25 02:29:27 -07:00
Blaise Tine
f292e5003d quartus build fixes 2020-08-23 22:04:46 -07:00
Blaise Tine
0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
Blaise Tine
6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
Blaise Tine
cd29362d10 fixed FPU handshake, optimized writeback's critical path 2020-08-07 10:11:54 -07:00
Blaise Tine
836a735555 minor updates 2020-07-31 13:39:52 -07:00
Blaise Tine
c9755a0c48 lkg build with pipeline + FPU fixes 2020-07-31 09:29:44 -04:00
Blaise Tine
e0a9089647 floating point support fixes 2020-07-27 16:01:56 -04:00
Blaise Tine
1f63f9da25 new fpu implementation 2020-07-24 00:00:37 -04:00
Blaise Tine
577a5791dc pipeline refactoring 2020-07-20 08:04:04 -04:00
Blaise Tine
25f66e6490 pipeline refactoring 2020-07-19 05:03:47 -04:00
Blaise Tine
2de61b5982 get device caps from CSRs 2020-06-30 00:08:23 -07:00
Blaise Tine
cc84e0691c multicore fix 2020-05-10 08:30:04 -04:00
Blaise Tine
f142afac80 rtl refactoring 2020-05-04 20:12:05 -04:00
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69f607b73e rtl refactoring 2020-05-03 17:10:02 -04:00
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43d8922f64 minor update 2020-04-21 15:21:59 -04:00
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d85c0af5d6 remove tab spaces 2020-04-21 03:19:47 -04:00
Blaise Tine
20ae78f434 fix simX build 2020-04-21 01:31:32 -04:00
Blaise Tine
ba4e736782 RTL code refactoring 2020-04-21 01:03:37 -04:00
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d79e36912f fix opae build 2020-04-20 12:51:42 -07:00
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b76f8696bd removing *.vh file for opae build 2020-04-20 15:07:27 -04:00
Blaise Tine
1a2823da0d RTL code refactoring 2020-04-20 13:52:24 -04:00
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885869df4a adding DEBUG MACROS 2020-04-19 04:59:52 -04:00
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9b476f1e17 RTL code refactoring 2020-04-19 03:38:00 -04:00
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81745f08c9 added config.vh 2020-04-16 07:49:19 -04:00
Blaise Tine
fc155e1223 project directories reorganization 2020-04-14 06:35:20 -04:00