Commit Graph

22 Commits

Author SHA1 Message Date
Blaise Tine
3a266fc792 adding compiler tests to regression suite 2021-03-09 05:01:56 -08:00
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062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
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41f09ffb55 minor update - allow independent driver cleanup 2021-02-28 18:19:26 -08:00
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29cd2f5dff fixed register file initialization to zero synthesis inference 2020-12-10 00:27:56 -08:00
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707ba3760f minor update 2020-12-08 21:37:53 -08:00
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d5438fd591 merging perf counters 2020-12-08 21:02:39 -08:00
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14baec86d5 moved apae sources into rtl/afu 2020-12-08 04:59:11 -08:00
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d68b32cd60 minor update 2020-12-06 22:40:27 -08:00
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1795980a52 L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization 2020-11-21 09:47:56 -08:00
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e946d976e7 constant integration updates 2020-11-15 08:44:57 -08:00
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7529f72c5d fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags 2020-10-20 05:32:55 -07:00
Blaise Tine
32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
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4e1007e5b2 scope refactoring 2020-10-03 18:53:21 -04:00
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0fab1ddd92 adding support for verilator-driven AFU driver: vlsim 2020-09-08 13:05:26 -04:00
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112d8ab815 adding CSR support to rtlsim driver 2020-09-04 06:51:31 -04:00
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de0ff93fe5 minor cleanup 2020-06-19 09:25:24 -07:00
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68d9fc9a75 driver basic test and demo test refactoring 2020-06-19 09:12:07 -07:00
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e2e1b63e14 refactor synthesis scripts + fixed quartus ram read-after-write bypass 2020-06-16 11:45:47 -07:00
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75af29febb scope refactoring 2020-06-13 11:47:28 -07:00
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170c88f295 scope fixes 2020-06-08 04:25:28 -07:00
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106d707024 verilator suppor for opae (partial) 2020-06-03 06:22:49 -04:00
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12dc4d6874 refactoring fixes 2020-04-14 19:39:59 -04:00