Blaise Tine
c1e168fdbe
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
minor update
minor update
minor update
minor update
minor update
cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor updates
minor updates
minor update
minor update
2023-11-10 02:47:05 -08:00
Blaise Tine
d7737542e4
cache uuid support
2021-12-09 20:43:22 -05:00
Blaise Tine
41d7e6c63a
cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
2021-11-30 07:08:15 -05:00
Blaise Tine
fe862f64b1
dispatch refactoring
2021-10-19 15:16:00 -04:00
Blaise Tine
e248f744d5
Merge branch 'master' of https://github.com/vortexgpgpu/vortex
2021-10-19 03:07:13 -04:00
Blaise Tine
58a2140b92
merge update
2021-10-15 19:58:13 -07:00
Blaise Tine
e380ded5e1
Merge branch 'master' into graphics
2021-10-15 19:32:11 -07:00
Santosh Raghav Srivatsan
dd12d3f848
vortex tutorial assignment 5 solution
2021-10-15 18:25:54 -04:00
Blaise Tine
04249c3ee9
code refactoring for Vivado compatibility
2021-09-29 04:48:53 -04:00
Blaise Tine
a45261b530
code refactoring for Vivado compatibility
2021-09-29 03:24:17 -04:00
Blaise Tine
18c1dc2f0e
fixed interface modports
2021-09-28 02:42:04 -07:00
Blaise Tine
9f34b2944c
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
Blaise Tine
3d052e9428
fmax optimization bundle (250 MHz).
2021-09-08 02:26:39 -07:00
Blaise Tine
05bc970900
minor update
2021-09-07 23:57:14 -07:00
Blaise Tine
3e014c8285
fmax optimizations bundles
2021-09-06 01:36:57 -07:00
Blaise Tine
b52ace5142
area optimization bundle
2021-09-05 23:35:44 -07:00
Blaise Tine
a801a16062
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
Blaise Tine
b1eef0fb7c
warp scheduler optimization
2021-08-07 23:45:01 -07:00
Blaise Tine
b5af2065ee
fetch optimization
2021-08-07 12:57:14 -07:00
Blaise Tine
e4d9fd8a00
thread mask redesign
2021-08-05 17:32:58 -07:00
Blaise Tine
7b8fe11e6a
unused variables refactoring
2021-08-05 01:46:26 -07:00
Blaise Tine
bb1ceffadd
rebase master update
2021-07-30 21:03:14 -07:00
Blaise Tine
0319283ea7
minor update
2021-07-20 21:42:22 -07:00
Blaise Tine
8048796102
minor update
2021-07-20 21:23:31 -07:00
Blaise Tine
aa7b0da877
minor update
2021-07-20 21:07:41 -07:00
Blaise Tine
d3b788784a
memory interface refactoring
2021-07-20 21:06:55 -07:00
Blaise Tine
382585d33d
minor update
2021-07-17 07:22:16 -07:00
Blaise Tine
5c40422e4f
dcache response bus optimization
2021-07-12 10:14:48 -07:00
Blaise Tine
c6afc35989
adding data fence support
2021-06-28 06:12:18 -07:00
Blaise Tine
f84c8a0b5d
instr_sched => ibuffer
2021-06-27 19:36:43 -07:00
Blaise Tine
1ea738ed26
lkg build
2021-06-25 16:28:10 -07:00
Blaise Tine
3cc1190cd7
CSRs I/O refactoring
2021-06-11 03:08:07 -07:00
Blaise Tine
5d2437d887
refactoring cache_config
2021-05-27 14:41:46 -07:00
Blaise Tine
8410c49f53
code refactoring: DRAM => MEM renaming
2021-04-26 00:58:48 -07:00
Blaise Tine
d808aa2735
perf counters generic size
2021-04-25 21:15:24 -07:00
Blaise Tine
10a994d11a
csr minor update
2021-03-08 03:46:07 -08:00
Blaise Tine
062d02ddce
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
Blaise Tine
b441870789
rename use_imm and use_PC
2021-03-01 00:38:46 -08:00
Blaise Tine
e64996946d
using 44-bit perf counters - aligned with DSP counters width
2021-02-28 02:05:47 -08:00
Blaise Tine
700f9eea19
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
Blaise Tine
ab63ac9e5d
cache request interfaces update
2021-02-10 20:55:04 -08:00
Blaise Tine
7c4823e65c
fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
2021-01-11 23:55:09 -08:00
Blaise Tine
9f128085d5
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
Blaise Tine
703a861fe9
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
Blaise Tine
d956e268b9
adding new performance counters (banks utilization and DRAM bus utilization)
2020-12-22 12:33:45 -08:00
Blaise Tine
4b7d871d62
allowing partial cache request submissions, io bus support broken
2020-12-21 03:53:13 -08:00
Blaise Tine
4bbd7bf408
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
Blaise Tine
fe07ca9aee
minor update
2020-12-09 05:49:02 -08:00
Blaise Tine
d5438fd591
merging perf counters
2020-12-08 21:02:39 -08:00
Xandy Liu
1595ff08e2
PERF pipeline stalls and cache
2020-12-08 01:14:41 -05:00
