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2 Commits

Author SHA1 Message Date
Lingjun Zhu
50d567d70c Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation 2019-10-28 14:49:55 -04:00
Lingjun Zhu
93531715bb Created a testbench and simulated the read/write of the register file 2019-10-18 22:55:34 -04:00