felsabbagh3
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ad45758a35
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Before Fetch->FE
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2019-09-08 18:09:11 -04:00 |
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felsabbagh3
|
c310e7381f
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Icache interface
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2019-09-08 17:36:09 -04:00 |
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felsabbagh3
|
5e6804703f
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Decode in FE
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2019-09-08 17:24:51 -04:00 |
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felsabbagh3
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ac9b06bf7d
|
Before FE BE abstraction
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2019-09-08 16:21:37 -04:00 |
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felsabbagh3
|
fe09aafbb4
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Interface Checkpoint 2 - Remove Lints
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2019-09-05 19:32:37 -04:00 |
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felsabbagh3
|
2d0e41db63
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checkpoint: Added icache struct
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2019-09-03 16:19:06 -04:00 |
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felsabbagh3
|
b216da5a6a
|
ram stdint + Quartus Files
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2019-06-11 21:13:30 -07:00 |
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felsabbagh3
|
d7afef04a9
|
Sim Work miss
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2019-05-18 23:42:55 +04:00 |
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felsabbagh3
|
48468ed26a
|
Proper SIMT with fine-grain scheduler implemented
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2019-05-10 00:49:54 -07:00 |
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felsabbagh3
|
79356c7ab1
|
Changed hierarchy + Identified private + public modules
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2019-05-07 23:45:05 -07:00 |
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felsabbagh3
|
191ed73415
|
Less expensive but slower fetch logic
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2019-05-05 22:55:47 -04:00 |
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felsabbagh3
|
f21eaec79f
|
Provisioned SM
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2019-04-05 19:25:54 -04:00 |
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felsabbagh3
|
166b9ae48d
|
Before Scratchpad
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2019-04-05 17:56:05 -04:00 |
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felsabbagh3
|
c83ef94d02
|
1 WARP 2 THREADS WORKING
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2019-03-31 05:02:55 -04:00 |
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felsabbagh3
|
99a0792a0c
|
Passing all tests with 2 threads
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2019-03-30 03:54:20 -04:00 |
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felsabbagh3
|
d02c3d25b7
|
sync
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2019-03-27 13:52:13 -04:00 |
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felsabbagh3
|
cc0fb0eece
|
better use of valid signal
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2019-03-27 00:07:59 -04:00 |
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felsabbagh3
|
7a528c5ef2
|
Packing data wires + ALU module
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2019-03-26 19:17:11 -04:00 |
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