78 Commits

Include renames

Author	SHA1	Message	Date
Blaise Tine	031d24e695	minor updates	2023-12-30 00:52:44 -08:00
Blaise Tine	e217bc2c23	adding tracking for SFU stalls	2023-12-28 12:12:11 -08:00
Blaise Tine	c7a81d1493	adding sockets support to simx and cache subsystem refactoring ... minor update minor update minor updates	2023-12-20 15:16:12 -08:00
Blaise Tine	914b680aed	operands optimization ... minor updates minor updates minor update operands optimization minor updates minor updates	2023-12-20 15:07:23 -08:00
Blaise Tine	e04e026a14	profiling update ... minor updates	2023-12-18 04:43:44 -08:00
Blaise Tine	c6845a4c8d	profiling timing optimization ... minor update minor update minor update	2023-12-18 04:43:10 -08:00
Blaise Tine	f5f9e3dfdb	profiling timing optimization	2023-12-18 04:43:10 -08:00
Blaise Tine	6c7ac35054	profiling optimizations ... minor updates	2023-12-18 04:43:00 -08:00
Blaise Tine	e5b41bcd66	wctl unit bug fix	2023-12-05 04:57:52 -08:00
root	900a1efaca	BUFFER_EX refactoring	2023-12-05 04:55:50 -08:00
Blaise Tine	e8d56dc013	minor update	2023-11-27 22:16:36 -08:00
Hansung Kim	5e5c625759	Write 0 instead of x for VX_CSR_MPM_RESERVED ... Otherwise it makes verification hard with tools that don't process x's well.	2023-11-27 16:06:16 -08:00
Hansung Kim	f41b50fc07	Define DBG_TRACE_CORE_PIPELINE_VCS for selective debug trace	2023-11-27 16:05:15 -08:00
Blaise Tine	24973ffca0	scoreboard optimization & profiling	2023-11-27 05:53:36 -08:00
Blaise Tine	ebec982434	minor update	2023-11-27 02:04:53 -08:00
Blaise Tine	43154cf738	minor updates	2023-11-16 23:41:59 -08:00
Hansung Kim	963c2765d9	Move force-include of gpu_pkg to non-cache modules	2023-11-15 22:02:44 -08:00
Hansung Kim	7e0b63a3b3	Change result type for dpi calls from wire -> reg ... VCS requires the output of the dpi calls to be of a type that can come at the LHS of a procedural assignment, i.e. reg type. Seems to be a different requirement from Verilator.	2023-11-15 19:26:12 -08:00
Blaise Tine	2c94e358b8	perf counter bug fix	2023-11-15 00:52:39 -08:00
Hansung Kim	20a9e6d102	Force include VX_gpu_pkg as compile order workaround ... addResource() calls in Chisel BlackBox does not preserve order of the files being included; the actual compile order for these files are re-arranged to be in alphabetical order. Therefore, while VX_gpu_pkg.sv has to be compiled before all the other modules because it holds the top-level package definition, that order cannot be ensured from Chisel. As a hacky workaround, simply `include this file in some of the sv files whose name starts earlier than VX_gpu_pkg in lexicographical order.	2023-11-14 23:00:43 -08:00
Blaise Tine	b274b8cc21	minor updates	2023-11-13 00:23:15 -08:00
Blaise Tine	a08d3ebd42	minor update	2023-11-12 23:40:59 -08:00
Blaise Tine	c1e168fdbe	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update	2023-11-10 02:47:05 -08:00
Blaise Tine	d13c5f2986	hw unit tests fixes	2023-11-05 18:51:31 -08:00
Blaise Tine	1fd5a95f5a	minor update	2023-11-03 18:04:05 -04:00
Blaise Tine	c9e6518e05	cache bindings and memory perf refactory	2023-11-03 08:18:18 -04:00
Blaise Tine	1c100c4cf5	minor update	2023-10-22 23:31:58 -07:00
Blaise Tine	d47cccc157	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes	2023-10-19 20:51:22 -07:00