fares
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19dba43849
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vecadd bug fixing + ebreak for termination
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2019-11-15 14:18:45 -05:00 |
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fares
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3d5120640b
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clCreateProgramWithBuiltInKernels OpenCL Error
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2019-11-15 01:14:31 -05:00 |
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felsabbagh3
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31de18c328
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Changed tb
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2019-11-10 15:06:06 -05:00 |
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felsabbagh3
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fbf708e419
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Started simX
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2019-11-10 01:21:09 -05:00 |
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Lyons, Ethan Tyler
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1c21110ffe
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Add files via upload
ICache_In_Place
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2019-11-08 10:56:11 -05:00 |
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felsabbagh3
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58a9140f08
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Before evict_wb_old removal
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2019-11-07 13:27:38 -05:00 |
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felsabbagh3
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9e2de897f0
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Added simple_main
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2019-11-07 00:10:06 -05:00 |
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Savan Roshan
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cb1bf65017
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Parameterization working
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2019-11-06 11:12:27 -05:00 |
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Savan Roshan
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8468e7d4d9
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Added prefix DCACHE_
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2019-11-05 08:33:38 -05:00 |
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Savan Roshan
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1db160a289
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Fixed parameterization
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2019-11-04 14:32:02 -05:00 |
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Savan Roshan
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8264339853
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Added Parameterization
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2019-11-04 13:20:34 -05:00 |
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felsabbagh3
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a39979a844
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Fixed ASIC GPR warp number delay
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2019-11-03 15:56:18 -05:00 |
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felsabbagh3
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bbb2373919
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Intrinsics: tests for TMC+Control Divergence
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2019-11-01 21:53:37 -04:00 |
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felsabbagh3
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46b09028d0
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Added runtime (kernel 2.0)
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2019-10-30 23:40:01 -04:00 |
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felsabbagh3
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06e5f6df1d
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Init num cycles
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2019-10-30 15:18:52 -04:00 |
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felsabbagh3
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7863175233
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Set associative bank working
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2019-10-30 14:57:20 -04:00 |
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felsabbagh3
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3b49b82c46
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GPR ASIC Working
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2019-10-29 23:20:16 -04:00 |
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felsabbagh3
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4aa04e76e6
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Simulate debug
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2019-10-29 14:28:20 -04:00 |
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felsabbagh3
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1b7f28273b
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Removed -O3 from makefile
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2019-10-27 20:34:32 -04:00 |
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felsabbagh3
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0ee74bc566
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migrated 100% to modelsim
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2019-10-27 20:08:44 -04:00 |
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felsabbagh3
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715982cca7
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Modelsim Working + Simulating + dumping - Some bugs
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2019-10-27 03:36:02 -04:00 |
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felsabbagh3
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372c81d90c
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Generate VCD with ModelSim
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2019-10-26 19:35:21 -04:00 |
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felsabbagh3
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6fda88b68f
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Modelsim Makefile compile + simulate - DPI
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2019-10-26 19:01:49 -04:00 |
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Elsabbagh
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9110e8367e
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modelsim
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2019-10-25 23:41:34 -04:00 |
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