Commit Graph

4 Commits

Author SHA1 Message Date
Hansung Kim
9651cc6bc5 Fix wrong dcache tag width in wrapper
Need to use DCACHE_NOSM_TAG_WIDTH instead of DCACHE_TAG_WIDTH; otherwise, the
`ASSIGN_VX_MEM_BUS_IF macro in VX_smem_unit.sv does assignment of packed structs
with different widths for the tag field, resulting in misaligned bit error.
This results in wrong memory addresses for the core requests.
2023-11-17 17:12:41 -08:00
Hansung Kim
e2d3d93dea Properly initialize DCR in wrapper code 2023-11-16 17:59:57 -08:00
Hansung Kim
963c2765d9 Move force-include of gpu_pkg to non-cache modules 2023-11-15 22:02:44 -08:00
Hansung Kim
448a253af3 Add Verilog wrapper module for VX_core 2023-11-15 20:09:53 -08:00