felsabbagh3
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8d143d7739
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Quartus + GPR evaluation
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2019-09-10 20:23:01 -04:00 |
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felsabbagh3
|
4e8da1811a
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New GPR structure - Clone or WSPAWN
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2019-09-09 22:17:20 -04:00 |
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felsabbagh3
|
1882147370
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GPR Wrapper Interface Done
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2019-09-09 14:04:07 -04:00 |
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felsabbagh3
|
bce9bc443c
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GPR Wrapper in Decode
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2019-09-09 01:03:13 -04:00 |
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felsabbagh3
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ecf81336db
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Finished FE and BE high-level
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2019-09-08 19:28:53 -04:00 |
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felsabbagh3
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981bf0afe5
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FE Done
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2019-09-08 18:36:47 -04:00 |
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felsabbagh3
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ad45758a35
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Before Fetch->FE
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2019-09-08 18:09:11 -04:00 |
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felsabbagh3
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5e6804703f
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Decode in FE
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2019-09-08 17:24:51 -04:00 |
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felsabbagh3
|
ac9b06bf7d
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Before FE BE abstraction
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2019-09-08 16:21:37 -04:00 |
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felsabbagh3
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fe09aafbb4
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Interface Checkpoint 2 - Remove Lints
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2019-09-05 19:32:37 -04:00 |
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felsabbagh3
|
2d0e41db63
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checkpoint: Added icache struct
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2019-09-03 16:19:06 -04:00 |
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felsabbagh3
|
b216da5a6a
|
ram stdint + Quartus Files
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2019-06-11 21:13:30 -07:00 |
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felsabbagh3
|
d7afef04a9
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Sim Work miss
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2019-05-18 23:42:55 +04:00 |
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felsabbagh3
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48468ed26a
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Proper SIMT with fine-grain scheduler implemented
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2019-05-10 00:49:54 -07:00 |
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felsabbagh3
|
96dac5e1ce
|
Warp + Context Aware Design - Global Stalling
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2019-05-08 16:32:49 -07:00 |
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felsabbagh3
|
a6c13bc38c
|
Inefficient context aware desgin
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2019-05-08 15:55:06 -07:00 |
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felsabbagh3
|
79356c7ab1
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Changed hierarchy + Identified private + public modules
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2019-05-07 23:45:05 -07:00 |
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felsabbagh3
|
191ed73415
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Less expensive but slower fetch logic
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2019-05-05 22:55:47 -04:00 |
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felsabbagh3
|
f21eaec79f
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Provisioned SM
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2019-04-05 19:25:54 -04:00 |
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felsabbagh3
|
719ed25213
|
Cleanup
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2019-03-31 16:30:37 -04:00 |
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felsabbagh3
|
8c2ae97510
|
1 WARP 8 THREADS TESTED + FULLY WORKING
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2019-03-31 05:21:00 -04:00 |
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felsabbagh3
|
c83ef94d02
|
1 WARP 2 THREADS WORKING
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2019-03-31 05:02:55 -04:00 |
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felsabbagh3
|
4aac33b298
|
Using verilog For-loops + Passing all tests
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2019-03-30 22:55:13 -04:00 |
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felsabbagh3
|
52a839f84d
|
Using verilog For-loops + Passing all tests
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2019-03-30 22:14:44 -04:00 |
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felsabbagh3
|
a3a3b21de7
|
Using verilog For-loops + Passing all tests
|
2019-03-30 22:09:03 -04:00 |
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felsabbagh3
|
99a0792a0c
|
Passing all tests with 2 threads
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2019-03-30 03:54:20 -04:00 |
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felsabbagh3
|
d02c3d25b7
|
sync
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2019-03-27 13:52:13 -04:00 |
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felsabbagh3
|
68f3ba84e5
|
Added HW threads - Infinite loop + fixed valid
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2019-03-27 03:53:59 -04:00 |
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felsabbagh3
|
9b42e79dcf
|
Added HW threads - Infinite loop
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2019-03-27 03:44:14 -04:00 |
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felsabbagh3
|
cc0fb0eece
|
better use of valid signal
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2019-03-27 00:07:59 -04:00 |
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felsabbagh3
|
7a528c5ef2
|
Packing data wires + ALU module
|
2019-03-26 19:17:11 -04:00 |
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