Blaise Tine
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8aa2d74714
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fixed Modelsim build errors
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2020-03-26 03:54:23 -04:00 |
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Blaise Tine
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07c52d8729
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code refactoring
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2020-03-26 03:20:46 -04:00 |
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Blaise Tine
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bf3d1fb5a2
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code refactoring
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2020-03-26 01:41:01 -04:00 |
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felsabbagh3
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82ea79c680
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Fix for Single-Threaded
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2020-03-22 14:44:46 -07:00 |
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wgulian3
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f565d47844
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revert saxpy change and fix stage_1_cycles not working
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2020-03-20 04:49:02 -04:00 |
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wgulian3
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5b3df797a4
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Add modified RTL files for parameterized builds with VX_define_synth.v
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2020-03-20 04:04:15 -04:00 |
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felsabbagh3
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0f5528a229
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Removed L3 for synthesis
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2020-03-13 15:01:46 -07:00 |
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wgulian3
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a931b588c2
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minor tweaks to appease quartus
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
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2020-03-10 12:15:30 -04:00 |
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felsabbagh3
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ca62e57a0d
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L3 and CLUSTRING WORKS
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2020-03-10 02:41:47 -07:00 |
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felsabbagh3
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dea271eb6b
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Fixed Stall Pipeline Logic
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2020-03-09 22:08:46 -07:00 |
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felsabbagh3
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469334f23e
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MULTICORE WITH L2 WORKING
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2020-03-09 01:17:11 -07:00 |
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felsabbagh3
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6c52b3d09b
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Added Shared Memory
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2020-03-08 15:00:53 -07:00 |
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felsabbagh3
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f315a8a44d
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Icache working
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2020-03-08 13:59:35 -07:00 |
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felsabbagh3
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4ed62f1aad
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Fixed all Cache Warnings
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2020-03-07 14:34:05 -08:00 |
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felsabbagh3
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db11bf6990
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Made the cache module configurable for multi-instantiation
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2020-03-07 00:49:40 -08:00 |
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Blaise Tine
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369c2c625c
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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felsabbagh3
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aa1a0ee376
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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3a45375596
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Fixed Verilator
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2020-02-17 19:36:00 -08:00 |
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fares
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9e58bf8fb5
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Started synthesis script
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2019-11-22 00:32:19 -05:00 |
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fares
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8acc32372b
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8Warp 32Threads for GTCAD synthesis
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2019-11-21 23:51:11 -05:00 |
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fares
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c4d315dfed
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VCD for power
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2019-11-21 23:25:51 -05:00 |
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Lyons, Ethan Tyler
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c8abd48458
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Synthesis Compatible
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2019-11-21 21:42:34 -05:00 |
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Lyons, Ethan Tyler
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509850192c
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Warps/Threads Parameterization
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2019-11-21 01:14:50 -05:00 |
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felsabbagh3
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70651f0340
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Added a pipeline stage + fixed SM param errors
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2019-11-13 12:25:28 -05:00 |
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Lyons, Ethan Tyler
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2994e607e3
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Shared Memory Implemented
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2019-11-13 10:06:13 -05:00 |
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felsabbagh3
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ef83285c6c
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FileIO Schema started
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2019-11-12 00:31:30 -05:00 |
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felsabbagh3
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7ed88ce4c1
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Fixed AA d_cache sizing errors
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2019-11-11 15:20:58 -05:00 |
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felsabbagh3
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4b2ea58b79
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Syn prep
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2019-11-11 14:20:15 -05:00 |
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felsabbagh3
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b3c7ac435a
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added sm defines
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2019-11-10 14:01:54 -05:00 |
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felsabbagh3
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fbf708e419
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Started simX
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2019-11-10 01:21:09 -05:00 |
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felsabbagh3
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ea7bd485ca
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Icache/Dcache finally done + configurability tested:
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2019-11-09 00:03:15 -05:00 |
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felsabbagh3
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8b81989bfd
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Before way logic change
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2019-11-08 18:16:40 -05:00 |
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Lyons, Ethan Tyler
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b0f685c2e2
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Add files via upload
ICache_In_Place
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2019-11-08 10:55:08 -05:00 |
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felsabbagh3
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58a9140f08
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Before evict_wb_old removal
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2019-11-07 13:27:38 -05:00 |
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Savan Roshan
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e4ee2a9cbd
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Parameterization working
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2019-11-07 00:14:46 -05:00 |
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Savan Roshan
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3a71a2ebdb
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Fixed bugs in parameterization
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2019-11-06 01:09:30 -05:00 |
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Savan Roshan
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8468e7d4d9
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Added prefix DCACHE_
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2019-11-05 08:33:38 -05:00 |
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Savan Roshan
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8264339853
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Added Parameterization
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2019-11-04 13:20:34 -05:00 |
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felsabbagh3
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3b49b82c46
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GPR ASIC Working
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2019-10-29 23:20:16 -04:00 |
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felsabbagh3
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4aa04e76e6
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Simulate debug
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2019-10-29 14:28:20 -04:00 |
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felsabbagh3
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7af6575b97
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SYN=1
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2019-10-28 13:57:01 -04:00 |
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felsabbagh3
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a8d063e9ad
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Synthesis Cleanup 1
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2019-10-28 13:43:12 -04:00 |
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felsabbagh3
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c85c01e082
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Parametized cache
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2019-10-25 13:36:06 -04:00 |
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felsabbagh3
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1e648c5819
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FIxed first circular issue
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2019-10-24 10:38:04 -04:00 |
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felsabbagh3
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1645a04b1d
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Fixed SM + added def SYN
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2019-10-22 15:56:30 -04:00 |
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felsabbagh3
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9d8273afe4
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Finished Cache Integration
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2019-10-22 06:02:08 -04:00 |
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felsabbagh3
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b3f464dd89
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Barriers impl + tested
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2019-10-22 01:47:39 -04:00 |
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felsabbagh3
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e67310acfb
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New Warp Scheduler + VCD Enable
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2019-09-15 00:12:41 -04:00 |
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felsabbagh3
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b216da5a6a
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ram stdint + Quartus Files
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2019-06-11 21:13:30 -07:00 |
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felsabbagh3
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d7afef04a9
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Sim Work miss
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2019-05-18 23:42:55 +04:00 |
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