Blaise Tine
|
4bbd7bf408
|
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
|
2020-12-19 02:45:06 -08:00 |
|
Blaise Tine
|
1795980a52
|
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
|
2020-11-21 09:47:56 -08:00 |
|
Blaise Tine
|
49b86c4b2a
|
SCOPE update
|
2020-09-05 10:52:59 -07:00 |
|
Blaise Tine
|
6c12391338
|
pipeline refactoring - fmax >= 222 mhz
|
2020-08-14 21:50:14 -07:00 |
|
Blaise Tine
|
7c86b68977
|
pipeline refactoring: centralized issue buffer
|
2020-07-26 11:21:08 -04:00 |
|
Blaise Tine
|
dc7efbcfb4
|
pipeline refactoring
|
2020-07-21 05:22:47 -04:00 |
|
Blaise Tine
|
25f66e6490
|
pipeline refactoring
|
2020-07-19 05:03:47 -04:00 |
|