5 Commits

Author	SHA1	Message	Date
Blaise Tine	1795980a52	L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization	2020-11-21 09:47:56 -08:00
Blaise Tine	49b86c4b2a	SCOPE update	2020-09-05 10:52:59 -07:00
Blaise Tine	0b355f228e	ibuffer addition	2020-08-22 00:22:04 -07:00
Blaise Tine	6c12391338	pipeline refactoring - fmax >= 222 mhz	2020-08-14 21:50:14 -07:00
Blaise Tine	8976100025	floating point support fixes	2020-07-28 04:19:46 -04:00