4 Commits

Author	SHA1	Message	Date
Blaise Tine	10505caae1	refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2	2020-11-08 01:31:46 -08:00
Blaise Tine	0a45a8beb3	minor update	2020-09-01 00:56:10 -07:00
Blaise Tine	ff7f65bd1f	opae build fixes	2020-07-21 05:44:13 -07:00
Blaise Tine	a70562d386	set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18	2020-06-29 08:03:19 -07:00