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0dfdf6cd4d
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-09-10 06:03:32 -04:00 |
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18172fa611
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AXI memory bus support
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2021-09-10 01:36:01 -07:00 |
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170c5d0c8a
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regression script update
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2021-09-08 23:22:50 -04:00 |
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c06efbf480
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minor update
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2021-09-07 23:47:41 -07:00 |
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53c8cddccf
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LKG build - minor update
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2021-08-30 10:25:52 -07:00 |
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90b50277d0
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cache multi-porting fixes + optimization
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2021-08-29 18:33:49 -07:00 |
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12b8b4af24
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minor updates
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2021-08-28 15:21:40 -07:00 |
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cc259f60f6
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minor update
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2021-08-11 15:39:21 -07:00 |
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90fa9eee7d
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minor update
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2021-08-08 18:35:05 -07:00 |
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91d4419fae
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new regression tests
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2021-08-02 16:05:33 -07:00 |
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6f0b5865e2
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minor update
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2021-07-25 02:35:34 -07:00 |
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c461b66b59
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fix debug log gathering on failure
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2021-07-24 10:20:05 -07:00 |
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4ffbcb336f
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minor update
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2021-07-22 14:20:02 -07:00 |
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152d807301
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parallelizing continious integration
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2021-07-20 12:12:11 -07:00 |
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b0d8adc82b
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minor update
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2021-07-16 06:44:28 -07:00 |
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5c40422e4f
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dcache response bus optimization
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2021-07-12 10:14:48 -07:00 |
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93fee18d59
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minor update
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2021-07-01 02:59:44 -07:00 |
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Blaise Tine
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22e201c07c
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-06-29 10:12:36 -04:00 |
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cd387d2b5b
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documentation udpate
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2021-06-29 07:04:27 -07:00 |
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44c82f6e13
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minor update
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2021-06-29 08:13:22 -04:00 |
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d2f9c66840
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minor update
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2021-06-29 03:50:01 -07:00 |
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79ebcc23d7
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minor update
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2021-06-29 03:45:57 -07:00 |
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e8c01e18d8
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regression fixes
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2021-06-29 04:32:32 -04:00 |
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24bde18cb1
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minor update
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2021-06-28 23:21:25 -07:00 |
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893bfd8e00
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minor update
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2021-06-28 06:05:25 -04:00 |
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1ea738ed26
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lkg build
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2021-06-25 16:28:10 -07:00 |
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2372067817
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minor update
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2021-06-22 09:30:36 -07:00 |
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e2743046a3
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minor update
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2021-06-14 01:07:47 -04:00 |
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585b31cc6d
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tests layout fixes
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2021-06-13 18:05:46 -07:00 |
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cadff791ab
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test layout fixes
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2021-06-13 17:59:06 -07:00 |
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03406c0a3f
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project tests refactoring
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2021-06-13 17:42:04 -07:00 |
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3071fb7a29
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adding support for non-cacheable memory addressing
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2021-06-06 13:35:55 -07:00 |
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df7d91d690
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more testing
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2021-05-26 15:29:39 -07:00 |
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9b120e3bb4
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minor update
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2021-05-24 20:05:36 -07:00 |
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c81b1173b8
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minor update
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2021-05-24 18:20:46 -07:00 |
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6107bf8247
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minor fix
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2021-05-04 11:05:07 -07:00 |
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962e193563
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blackbox update
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2021-05-03 07:45:39 -07:00 |
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bac53e4ae1
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minor update
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2021-05-02 11:05:49 -07:00 |
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d504adb236
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afu mem controller refactoring
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2021-05-01 08:39:52 -07:00 |
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95f057bc2e
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fpga build refactoring
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2021-04-29 06:17:28 -07:00 |
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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4cb98a25a7
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enabling 128-bit dram bus
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2021-04-24 00:31:27 -04:00 |
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41413a51ba
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testing no-shared memory mode
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2021-04-01 12:37:40 -07:00 |
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79d1d309a5
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llvm-riscv toolchain update
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2021-03-09 08:11:59 -08:00 |
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28d51e0cf9
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minor update
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2021-03-09 05:50:23 -08:00 |
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3a266fc792
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adding compiler tests to regression suite
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2021-03-09 05:01:56 -08:00 |
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848fc0c2df
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minor update
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2021-03-09 00:07:05 -08:00 |
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907e6868cd
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simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite
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2021-03-08 23:58:33 -08:00 |
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41f09ffb55
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minor update - allow independent driver cleanup
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2021-02-28 18:19:26 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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