Commit Graph
17 Commits
Author SHA1 Message Date
Blaise Tine 10505caae1 refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2 2020-11-08 01:31:46 -08:00
Blaise Tine 5be1d85648 cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count 2020-11-02 01:50:12 -08:00
Blaise Tine 9a9f7955f0 basic test timing + scope tracing ccip 2020-10-27 17:04:04 -04:00
Blaise Tine 32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
Blaise Tine 49b86c4b2a SCOPE update 2020-09-05 10:52:59 -07:00
Blaise Tine b211b29670 removing pipeline additional registers 2020-08-25 14:02:35 -07:00
Blaise Tine 57971f6c76 decode op_mod optimization 2020-08-24 02:55:14 -07:00
Blaise Tine f292e5003d quartus build fixes 2020-08-23 22:04:46 -07:00
Blaise Tine 0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
Blaise Tine 6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
Blaise Tine 27e95530ef pipeline optimization 2020-07-30 03:06:01 -07:00
Blaise Tine 8976100025 floating point support fixes 2020-07-28 04:19:46 -04:00
Blaise Tine 7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
Blaise Tine 75e3c31b56 fpu implementation (part1) 2020-07-23 03:18:09 -07:00
Blaise Tine dc7efbcfb4 pipeline refactoring 2020-07-21 05:22:47 -04:00
Blaise Tine 577a5791dc pipeline refactoring 2020-07-20 08:04:04 -04:00
Blaise Tine 25f66e6490 pipeline refactoring 2020-07-19 05:03:47 -04:00