Hansung Kim
4cac1adf7d
Add dummy code for decoupled Hopper tensor core
...
Define EXT_T_HOPPER that, when EXT_T_ENABLE is defined, distinguishes
whether to instantiate core-coupled Volta-style or decoupled
Hopper-style Tensor Core.
2024-10-07 17:10:59 -07:00
Richard Yan
3f8c28c7d6
sync rf, x0 fix
2024-09-05 16:49:05 -07:00
Hansung Kim
d4f6f8a257
Set NUM_ALU_BLOCKS=2, NUM_FPU_BLOCKS=1
2024-06-22 16:33:42 -07:00
Hansung Kim
a9b75dd492
Set default to 4cores/8barriers in VX_config.{h,vh}
2024-06-12 20:51:15 -07:00
Hansung Kim
35273b3d74
Set correct dpu hmma latency
2024-05-29 17:14:54 -07:00
Hansung Kim
28f6cd59b5
tensor: Improve commit efficiency by decoupling dpu with fifo
2024-05-26 22:00:25 -07:00
Hansung Kim
5034d8d14b
tensor: Add buffer to hide 2cyc commit latency
...
Since operand and commit throughput are the same (2 cycles), it is
unnecessary to stall the dpu during the multi-cycle commit.
This enables the dpu to operate at full throughput of 1 operand every 2
cycles.
2024-05-16 20:09:08 -07:00
Hansung Kim
89e7d65926
tensor: Add ready signal to enforce 1 warp occupancy
...
Currently disabled as the timing behavior is already ~accurate
2024-05-16 15:34:54 -07:00
Richard Yan
d624b3e50a
store fencing, large smem, fix tensor core for firesim
2024-05-15 21:45:48 -07:00
Richard Yan
0dd5335851
fix merge error once again
2024-05-08 11:31:43 -07:00
Hansung Kim
f71e705d53
Revert to old LSUQ_SIZE
2024-05-07 16:23:32 -07:00
Richard Yan
4aad161739
Merge branch 'rtl' of https://github.com/hansungk/vortex-private into rtl
2024-05-07 14:00:31 -07:00
Richard Yan
1e5dff52c1
shrink queue sizes
2024-05-07 13:54:23 -07:00
Hansung Kim
675e8ea130
Merge branch 'tensor_core' into rtl
2024-05-01 16:18:14 -07:00
Hansung Kim
100fbbc048
Increase FPUQ_SIZE
...
This should at least be FMA_LATENCY to not bottleneck things.
2024-04-29 15:19:48 -07:00
Richard Yan
17fd29c114
Merge branch 'rtl' of https://github.com/hansungk/vortex-private into rtl
2024-04-16 23:03:04 -07:00
Richard Yan
8de5470da4
round robin warp scheduling
2024-04-16 23:03:00 -07:00
Hansung Kim
4752b86858
Limit NUM_SFU_LANES to 4
...
Simulation seems to not like SFU_LANES=8; dial back for now
2024-04-15 21:48:59 -07:00
Richard Yan
41a79a03a4
parametrize memory interface in core wrapper and update config.vh
2024-04-09 19:55:06 -07:00
joshua
b254281295
initial tcore impl
2024-03-21 01:29:38 -07:00
joshua
f9b4509936
initial tensor core
2024-03-20 02:46:00 -07:00
joshua
978dd3bdfe
seemingly working fp32 implementation
2024-03-19 17:56:59 -07:00
Hansung Kim
b63333a4ec
Merge remote-tracking branch 'upstream/master' into vortex2
2024-03-07 14:45:48 -08:00
Blaise Tine
b0b7cd2b1e
minor updates
2024-02-03 19:09:53 -08:00
Hansung Kim
48558982f7
Merge remote-tracking branch 'upstream/master' into vortex2
2024-02-01 23:35:58 -08:00
Blaise Tine
38b92ad592
- using SV_DPI defines to disable DPI in synthesis-based simulations
...
- fixed Intel ASE run script: run_ase.sh
2024-01-28 00:22:21 -08:00
Hansung Kim
60d4180249
Increase LSUQ and IBUF size
2024-01-16 23:53:14 -08:00
Blaise Tine
031d24e695
minor updates
2023-12-30 00:52:44 -08:00
Blaise Tine
c7a81d1493
adding sockets support to simx and cache subsystem refactoring
...
minor update
minor update
minor updates
2023-12-20 15:16:12 -08:00
Blaise Tine
c6845a4c8d
profiling timing optimization
...
minor update
minor update
minor update
2023-12-18 04:43:10 -08:00
Blaise Tine
6c7ac35054
profiling optimizations
...
minor updates
2023-12-18 04:43:00 -08:00
Blaise Tine
d65cc61df5
minor update
2023-11-16 12:00:37 -08:00
Blaise Tine
547d916ae2
minor update
2023-11-15 13:00:06 -08:00
Blaise Tine
c1e168fdbe
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
minor update
minor update
minor update
minor update
minor update
cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor updates
minor updates
minor update
minor update
2023-11-10 02:47:05 -08:00
Blaise Tine
c9e6518e05
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
Blaise Tine
d47cccc157
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
Santosh Srivatsan
836c777680
XLEN parameterization for simx
2022-02-03 15:19:31 -05:00
Santosh Srivatsan
91c22a2592
Fixed some riscv-tests
2022-01-22 12:54:10 -05:00
Santosh Srivatsan
d762d401cd
Added 64-bit linker script
2022-01-11 17:22:16 -05:00
Santosh Srivatsan
e82d5fe48f
Removed all comments labelled \'simx64\'
2021-12-13 19:52:13 -05:00
Santosh Srivatsan
5edb9098ce
Merge branch 'simx64'
2021-12-10 21:48:29 -05:00
Santosh Raghav Srivatsan
f0dc04ad04
Added tests to commit. 64 bit simx still not working
2021-12-01 02:44:14 -05:00
Blaise Tine
4477cbeed1
blackbox caching fix
2021-11-30 15:36:59 -05:00
Blaise Tine
41d7e6c63a
cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
2021-11-30 07:08:15 -05:00
Blaise Tine
18762dffce
fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,
2021-11-24 00:00:17 -05:00
Blaise Tine
9656779d48
minor update
2021-11-14 04:45:06 -05:00
Blaise Tine
58a2140b92
merge update
2021-10-15 19:58:13 -07:00
Blaise Tine
e380ded5e1
Merge branch 'master' into graphics
2021-10-15 19:32:11 -07:00
Blaise Tine
9f34b2944c
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
Blaise Tine
4e8293c3e3
cache bank pipeline optimization
2021-09-14 02:09:35 -07:00
