felsabbagh3
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95047fcadc
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Rename Stage that removes the need for forwarding
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2019-10-17 00:48:54 -04:00 |
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felsabbagh3
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8bc3b8b0a5
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Need to link SystemC for sc_time_stamp()
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2019-10-14 23:25:14 -04:00 |
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felsabbagh3
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ee83e6d8c8
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Moved GPR to back-end
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2019-10-14 19:08:32 -04:00 |
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felsabbagh3
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e67310acfb
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New Warp Scheduler + VCD Enable
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2019-09-15 00:12:41 -04:00 |
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felsabbagh3
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fb3bc60189
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Finalized GPR with 3-Port Structure
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2019-09-11 14:53:32 -04:00 |
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felsabbagh3
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3c3a443bd5
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New RF with Evaluation
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2019-09-11 01:04:23 -04:00 |
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felsabbagh3
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fe09aafbb4
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Interface Checkpoint 2 - Remove Lints
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2019-09-05 19:32:37 -04:00 |
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felsabbagh3
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2d0e41db63
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checkpoint: Added icache struct
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2019-09-03 16:19:06 -04:00 |
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felsabbagh3
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b216da5a6a
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ram stdint + Quartus Files
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2019-06-11 21:13:30 -07:00 |
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felsabbagh3
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d7afef04a9
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Sim Work miss
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2019-05-18 23:42:55 +04:00 |
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felsabbagh3
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48468ed26a
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Proper SIMT with fine-grain scheduler implemented
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2019-05-10 00:49:54 -07:00 |
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felsabbagh3
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719ed25213
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Cleanup
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2019-03-31 16:30:37 -04:00 |
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felsabbagh3
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8c2ae97510
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1 WARP 8 THREADS TESTED + FULLY WORKING
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2019-03-31 05:21:00 -04:00 |
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felsabbagh3
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c83ef94d02
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1 WARP 2 THREADS WORKING
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2019-03-31 05:02:55 -04:00 |
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felsabbagh3
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a3a3b21de7
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Using verilog For-loops + Passing all tests
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2019-03-30 22:09:03 -04:00 |
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felsabbagh3
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99a0792a0c
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Passing all tests with 2 threads
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2019-03-30 03:54:20 -04:00 |
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felsabbagh3
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d02c3d25b7
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sync
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2019-03-27 13:52:13 -04:00 |
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felsabbagh3
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68f3ba84e5
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Added HW threads - Infinite loop + fixed valid
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2019-03-27 03:53:59 -04:00 |
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felsabbagh3
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9b42e79dcf
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Added HW threads - Infinite loop
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2019-03-27 03:44:14 -04:00 |
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felsabbagh3
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cc0fb0eece
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better use of valid signal
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2019-03-27 00:07:59 -04:00 |
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felsabbagh3
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01d142c6e6
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rtl passing all tests
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2019-03-22 02:44:53 -04:00 |
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felsabbagh3
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656475b3b3
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Passing Most tests
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2019-03-21 23:47:48 -04:00 |
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