felsabbagh3
|
b4d921f49a
|
set_top_level tcl
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2019-10-23 11:56:32 -04:00 |
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felsabbagh3
|
3cb5820ecd
|
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2019-10-22 13:19:00 -04:00 |
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felsabbagh3
|
f68942c92a
|
Added cache+shared memory search path
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2019-10-22 13:18:49 -04:00 |
|
Shim
|
c43b3800d8
|
added report power and save ddc to synthesis script
|
2019-10-22 11:27:13 -04:00 |
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felsabbagh3
|
9d8273afe4
|
Finished Cache Integration
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2019-10-22 06:02:08 -04:00 |
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felsabbagh3
|
b7af8c3f34
|
Integrated Shared Memory
|
2019-10-22 05:03:47 -04:00 |
|
felsabbagh3
|
1bfafca896
|
Cleanup before integration
|
2019-10-22 03:03:17 -04:00 |
|
Lingjun Zhu
|
eeb0a321a8
|
Finished synthesis with no optimization, cell count increasts to 100k
|
2019-10-21 17:53:51 -04:00 |
|
Lingjun Zhu
|
e2cd8102eb
|
Uncommented the necessary line about write_bit_mask on VX_gpr.v again, try synthesizing
|
2019-10-21 17:09:51 -04:00 |
|
felsabbagh3
|
fd876144f5
|
.tcl mod
|
2019-10-21 11:27:01 -04:00 |
|
felsabbagh3
|
bab1852a99
|
Added Split/Join - not tested
|
2019-10-21 03:03:15 -04:00 |
|
felsabbagh3
|
84f5ccb484
|
Added CSR TID/WID reads
|
2019-10-21 02:10:05 -04:00 |
|
felsabbagh3
|
f7b55427b4
|
Added ISA2 infrastructure with bugs
|
2019-10-18 05:21:32 -04:00 |
|
felsabbagh3
|
559c64cb36
|
Cleanup
|
2019-10-18 02:20:38 -04:00 |
|
felsabbagh3
|
505bbc20c8
|
Removed FWD
|
2019-10-18 02:01:39 -04:00 |
|
felsabbagh3
|
ccbb2acab5
|
LSU+EXU minor
|
2019-10-17 22:38:09 -04:00 |
|
felsabbagh3
|
6779d0fade
|
Instruction Multiplex LSU/EXU 1 cycle DONE
|
2019-10-17 22:29:21 -04:00 |
|
Lingjun Zhu
|
d164ebfbc6
|
Added log file of synthesis, too many registers are removed
|
2019-10-17 14:25:54 -04:00 |
|
Lingjun Zhu
|
a4d6ada16d
|
Fixed the issues of memory during synthesis
|
2019-10-17 14:18:52 -04:00 |
|
Shim
|
78e4067013
|
added log file
|
2019-10-17 14:00:22 -04:00 |
|
Shim
|
0bea82a2c3
|
added tcl file
|
2019-10-17 11:55:18 -04:00 |
|