Hansung Kim
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5a95eba1f5
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tensor: Clear c_*_tile before compute
This didn't really cause any problem, but just to be sure.
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2024-05-25 19:54:44 -07:00 |
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Hansung Kim
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89e7d65926
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tensor: Add ready signal to enforce 1 warp occupancy
Currently disabled as the timing behavior is already ~accurate
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2024-05-16 15:34:54 -07:00 |
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Hansung Kim
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9c1d797250
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tensor: add missing }
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2024-05-05 18:36:15 -07:00 |
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Hansung Kim
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9ea291eea2
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Merge remote-tracking branch 'origin/tensor_core' into rtl
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2024-05-05 17:03:57 -07:00 |
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joshua
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5bd25985c6
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i kinda forgot most of changes
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2024-05-04 23:01:47 -07:00 |
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Hansung Kim
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bc45c40231
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tensor: Rename half.hpp -> half.h
addResource() thinks it's a Verilog source file if it ends in .hpp, for
some reason.
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2024-05-02 16:17:20 -07:00 |
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Hansung Kim
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675e8ea130
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Merge branch 'tensor_core' into rtl
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2024-05-01 16:18:14 -07:00 |
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joshua
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978dd3bdfe
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seemingly working fp32 implementation
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2024-03-19 17:56:59 -07:00 |
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Hansung Kim
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bbacf9a25e
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Remove verilated vpi code, add missing includes for C++
Vortex rtlsim defines sim_trace_enabled... functions in the Verilated
C++ code for use in dpi_trace, which we don't need.
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2023-11-15 20:06:58 -08:00 |
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Blaise Tine
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d47cccc157
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Vortex 2.0 changes:
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
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2023-10-19 20:51:22 -07:00 |
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Santosh Srivatsan
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f93303bac7
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Minor update
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2021-12-15 17:21:38 -05:00 |
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Blaise Tine
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b8682f56ac
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softfloat library integration
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2021-10-10 13:20:50 -07:00 |
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Blaise Tine
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efb70b21df
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dpi bug fix
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2021-10-07 13:35:35 -04:00 |
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Blaise Tine
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d15e33e87f
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fpu dpi update
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2021-03-31 02:36:34 -07:00 |
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Blaise Tine
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2b8435471a
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speeding up simulation using dedicated full dpi-based FPU core
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2021-01-06 18:44:06 -08:00 |
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