Blaise Tine
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4e1007e5b2
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scope refactoring
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2020-10-03 18:53:21 -04:00 |
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Blaise Tine
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f6f95e0c46
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mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
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2020-09-19 14:45:42 -04:00 |
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Blaise Tine
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49b86c4b2a
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SCOPE update
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2020-09-05 10:52:59 -07:00 |
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Blaise Tine
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c63217f67d
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fixed SCOPE interface
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2020-09-01 05:20:13 -07:00 |
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Blaise Tine
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31ffbe0d6a
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clean up 'stage_1_cycles' from cache
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2020-09-01 03:39:03 -07:00 |
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Blaise Tine
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6c12391338
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pipeline refactoring - fmax >= 222 mhz
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2020-08-14 21:50:14 -07:00 |
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Blaise Tine
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83a1695c73
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OPAE CSR access
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2020-06-30 18:14:06 -07:00 |
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Blaise Tine
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582a00d690
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adding OPAE CSR support
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2020-06-30 10:05:57 -07:00 |
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felsabbagh3
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b8e8cab1ee
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Added CSR IO req/rsp V0.1
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2020-06-29 23:00:34 -07:00 |
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Blaise Tine
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8302641510
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fpga fixes
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2020-06-27 14:03:20 -07:00 |
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Blaise Tine
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5e718c2676
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refactoring
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2020-06-23 09:54:40 -07:00 |
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