Blaise Tine
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3071fb7a29
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adding support for non-cacheable memory addressing
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2021-06-06 13:35:55 -07:00 |
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Blaise Tine
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df7d91d690
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more testing
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2021-05-26 15:29:39 -07:00 |
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Blaise Tine
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9b120e3bb4
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minor update
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2021-05-24 20:05:36 -07:00 |
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Blaise Tine
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c81b1173b8
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minor update
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2021-05-24 18:20:46 -07:00 |
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Blaise Tine
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6107bf8247
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minor fix
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2021-05-04 11:05:07 -07:00 |
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Blaise Tine
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bac53e4ae1
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minor update
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2021-05-02 11:05:49 -07:00 |
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Blaise Tine
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d504adb236
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afu mem controller refactoring
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2021-05-01 08:39:52 -07:00 |
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Blaise Tine
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95f057bc2e
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fpga build refactoring
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2021-04-29 06:17:28 -07:00 |
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Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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Blaise Tine
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4cb98a25a7
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enabling 128-bit dram bus
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2021-04-24 00:31:27 -04:00 |
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Blaise Tine
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41413a51ba
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testing no-shared memory mode
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2021-04-01 12:37:40 -07:00 |
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Blaise Tine
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3a266fc792
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adding compiler tests to regression suite
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2021-03-09 05:01:56 -08:00 |
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Blaise Tine
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907e6868cd
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simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite
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2021-03-08 23:58:33 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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6a6711b735
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minor update
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2021-02-04 09:11:46 -08:00 |
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