Commit Graph

9 Commits

Author SHA1 Message Date
Lingjun Zhu
b6558714ca Finished synthesis with all memory but no optimization 2019-10-28 16:18:11 -04:00
Lingjun Zhu
0b30b3a35f Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data 2019-10-28 15:06:23 -04:00
felsabbagh3
a8d063e9ad Synthesis Cleanup 1 2019-10-28 13:43:12 -04:00
felsabbagh3
715982cca7 Modelsim Working + Simulating + dumping - Some bugs 2019-10-27 03:36:02 -04:00
felsabbagh3
1181af1df2 Modelsim basic sim 2019-10-26 00:34:57 -04:00
felsabbagh3
c85c01e082 Parametized cache 2019-10-25 13:36:06 -04:00
felsabbagh3
89d0390965 CACHE FINALLY WORKING 2019-10-25 04:01:23 -04:00
felsabbagh3
1645a04b1d Fixed SM + added def SYN 2019-10-22 15:56:30 -04:00
felsabbagh3
9d8273afe4 Finished Cache Integration 2019-10-22 06:02:08 -04:00