Commit Graph

4 Commits

Author SHA1 Message Date
Lingjun Zhu
50d567d70c Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation 2019-10-28 14:49:55 -04:00
felsabbagh3
b7af8c3f34 Integrated Shared Memory 2019-10-22 05:03:47 -04:00
Lingjun Zhu
405926f66f Generated memory blocks for data cache (data), data cache (tag), shared memory 2019-10-20 14:52:28 -04:00
Lingjun Zhu
84d321a517 Create the memory blocks with CLN28HPM 2019-10-17 15:38:48 -04:00