323ed7d7e9
Update Vortex core for Blackwell tensor instructions
...
- Add Blackwell tensor core support in VX_tensor_blackwell_core.sv
- Update decode, execute, and dispatch logic for new instructions
- Extend VX_define.vh and VX_types.vh with Blackwell ISA definitions
2026-05-06 14:50:54 +08:00
cb912d3b8b
Add Blackwell tensor RTL scaffolding
2026-04-25 10:15:31 +08:00
Hansung Kim
408a9b5d2a
tensor: Write stall logic for hgmma_wait
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HGMMA_WAIT instruction stalls at issue when inuse_tensor is set, which
is done by the previous HGMMA insn. Currently inuse_tensor is never set
back to zero.
2024-10-11 17:18:01 -07:00
joshua
f9b4509936
initial tensor core
2024-03-20 02:46:00 -07:00
joshua
beb3dce46d
integer reduction unit
2024-03-06 01:39:17 -08:00
Blaise Tine
b0b7cd2b1e
minor updates
2024-02-03 19:09:53 -08:00
Blaise Tine
8ab7c590fd
disabling fetch's deadlock check when L1 caches are present
2024-01-31 06:16:54 -08:00
Blaise Tine
e217bc2c23
adding tracking for SFU stalls
2023-12-28 12:12:11 -08:00
Blaise Tine
c7a81d1493
adding sockets support to simx and cache subsystem refactoring
...
minor update
minor update
minor updates
2023-12-20 15:16:12 -08:00
root
900a1efaca
BUFFER_EX refactoring
2023-12-05 04:55:50 -08:00
Blaise Tine
9f1f1ecaa3
minor update
2023-11-03 08:36:28 -04:00
Blaise Tine
c9e6518e05
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
Blaise Tine
d47cccc157
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
Blaise Tine
d7737542e4
cache uuid support
2021-12-09 20:43:22 -05:00
Blaise Tine
41d7e6c63a
cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
2021-11-30 07:08:15 -05:00
Blaise Tine
18762dffce
fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,
2021-11-24 00:00:17 -05:00
Blaise Tine
e248f744d5
Merge branch 'master' of https://github.com/vortexgpgpu/vortex
2021-10-19 03:07:13 -04:00
Blaise Tine
6edf38548f
text_unit merge fixes
2021-10-19 00:16:22 -04:00
Blaise Tine
58a2140b92
merge update
2021-10-15 19:58:13 -07:00
Blaise Tine
e380ded5e1
Merge branch 'master' into graphics
2021-10-15 19:32:11 -07:00
Santosh Raghav Srivatsan
dd12d3f848
vortex tutorial assignment 5 solution
2021-10-15 18:25:54 -04:00
Blaise Tine
a45261b530
code refactoring for Vivado compatibility
2021-09-29 03:24:17 -04:00
Blaise Tine
9f34b2944c
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
Blaise Tine
81bee3ac45
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-09-08 02:27:53 -07:00
Blaise Tine
aeeb3ca616
ALU unit critical path optimization
2021-09-07 23:54:10 -07:00
Blaise Tine
d3c3d551ff
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-08-31 03:36:37 -04:00
Blaise Tine
c162ce526f
adding predicate instruction
2021-08-31 03:23:59 -04:00
Blaise Tine
53c8cddccf
LKG build - minor update
2021-08-30 10:25:52 -07:00
Blaise Tine
a801a16062
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
Blaise Tine
90b50277d0
cache multi-porting fixes + optimization
2021-08-29 18:33:49 -07:00
Blaise Tine
12b8b4af24
minor updates
2021-08-28 15:21:40 -07:00
Blaise Tine
7202bdf977
minor update
2021-08-12 01:51:46 -07:00
Blaise Tine
dc322894cd
bug fixes - lkg build
2021-08-01 19:21:37 -07:00
Blaise Tine
bb1ceffadd
rebase master update
2021-07-30 21:03:14 -07:00
Blaise Tine
0319283ea7
minor update
2021-07-20 21:42:22 -07:00
Blaise Tine
201aa2c6ad
minor udpate
2021-06-28 09:14:06 -07:00
Blaise Tine
c6afc35989
adding data fence support
2021-06-28 06:12:18 -07:00
Blaise Tine
6ae2f5199d
decode optimization
2021-06-28 05:06:30 -07:00
Blaise Tine
41069ba188
non-cacheable memory address fixes
2021-06-06 20:54:36 -07:00
Blaise Tine
3071fb7a29
adding support for non-cacheable memory addressing
2021-06-06 13:35:55 -07:00
Blaise Tine
95f057bc2e
fpga build refactoring
2021-04-29 06:17:28 -07:00
Blaise Tine
8543e3a8bf
code refactoring
2021-04-26 02:34:21 -07:00
Blaise Tine
8410c49f53
code refactoring: DRAM => MEM renaming
2021-04-26 00:58:48 -07:00
Blaise Tine
d808aa2735
perf counters generic size
2021-04-25 21:15:24 -07:00
Blaise Tine
8a9a67aa5a
minor update
2021-02-27 21:54:55 -08:00
Blaise Tine
f5a17bd1a9
decode optimization and refactoring
2021-02-27 18:21:41 -08:00
Blaise Tine
700f9eea19
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
Blaise Tine
ab63ac9e5d
cache request interfaces update
2021-02-10 20:55:04 -08:00
Blaise Tine
fcbf57b66a
specialized shared memory module
2021-01-16 04:41:58 -08:00
Blaise Tine
7c4823e65c
fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
2021-01-11 23:55:09 -08:00
